Patterning of Miniaturized Oxide TFTs with High-Resolution Reverse-Offset Printing for Low-Voltage IoT Applications

Description

Oxide thin-film transistors (TFTs) are key electronic components applied in display backplanes and flat panel X-ray detectors due to their high mobility, low off current, and low temperature processing. Their use in back-end-of-line (BEOL) applications, in highly sensitive biosensors, and in flexible integrated circuits (ICs) are also under active research. Oxide TFTs can be fabricated using vacuum processes, such as sputtering and atomic layer deposition (ALD), as well as through low-cost, solution-based processes including printing. Critical to the implementation of such TFTs in flexible ICs for Internet-of-Things (IoT) and wearable applications are: (i) low-voltage operation (≤ 5 V) (enabling low power operation), (ii) small device size (≤ 5 μm) (avoiding impractically large circuit footprints and increasing yield), and (iii) high charge carrier mobility (≥ 10 cm2/(Vs)) (enabling sufficient operation frequency and/or gain).
We have developed a versatile, high-resolution patterning method of thin films that is based on reverse-offset printing (ROP) of a polymer resist at μm-level resolution. The technique can be used to fabricate both solution- and vacuum deposited oxide TFTs down to 2.5 μm channel lengths. The steep sidewalls of the printed polymer allow it to be employed as a sacrificial layer to pattern vacuum-deposited metal (e.g., Al, Cu, Ti/Au) via lift-off process. The patterned layers can be used both as gate and source/drain (S/D) contacts to the TFTs as well as sensor electrodes. This can help to avoid problems (e.g. stability) associated with S/D-contacts that are printed with nanoparticle inks. Moreover, we demonstrate that the same ROP resist can also be used as an etch mask to pattern a solution-processed, ALD-grown, or sputtered oxide semiconductor and gate dielectric thin films.
Here, we discuss the fabrication process and the electrical performance of n-type oxide TFTs with solution-processed In2O3 as well as ALD-grown ZnO and In2O3 semiconductors that are patterned using ROP down to 5 μm channel lengths. Depending on the semiconductor fabrication process and the device stack and geometry, we achieve TFTs that operate at ≤ 5 V and show ~3 – 10 cm2/(Vs) mobility, high ON/OFF-ratio >107, and turn-on voltage close to 0 V. By using unipolar pseudo-CMOS circuit topology, flexible ICs can be developed for IoT and wearable application, reducing the need for Si-chips. The use of benign and Earth-abundant materials palette, such as ZnO, enables the development of sustainable IoT sensor platforms.

Period	5 Dec 2024
Event title	2024 MRS Fall Meeting
Event type	Conference
Location	Boston, United States, MassachusettsShow on map
Degree of Recognition	International