Abstract
This paper focuses on the design aspects of the key components for a scalable phased-array system over the 200 GHz frequency range. A high-gain phase shifter chain for 220 to 240 GHz frequency range and a high-gain power amplifier (PA) with a high output power are designed in a 0.13-$\mu\text{m}$ SiGe BiCMOS technology. The phase shifter chain includes a low-noise amplifier (LNA), a vector modulator phase shifter (PS), and a gain-enhancing amplifier. The LNA is a five-stage cascode design. The vector modulator core is realized by two variable gain amplifiers based on the Gilbert cell architecture. A four-stage cascode design is used for the gain-enhancing amplifier. The phase shifter chain shows a measured gain of 18 dB at 230 GHz with a $360 {\mathrm { ^{\circ}}}$ phase tuning range and more than 10 dB of gain control. The chip achieves a minimum measured noise figure of 11.5 dB at 230 GHz and shows a wideband noise characteristic. The complete phase shifter chain chip consumes a dc power of 153 mW and occupies a 1.41 mm2 area. A high-power PA that is critical for a large phased-array system is designed. This paper presents a unique 4-way power combining technique utilizing a differential quadrature coupler. The realized balanced PA occupies an area of 0.67 mm2 and shows a measured peak gain of 21 dB at 244 GHz. The PA consumes 819 mW of dc power and delivers a maximum saturated output power (P sat) of 7.1 dBm at 244 GHz and more than 4.3 dBm of P sat from 230 to 255 GHz.
Original language | English |
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Pages (from-to) | 23565-23577 |
Number of pages | 13 |
Journal | IEEE Access |
Volume | 11 |
DOIs | |
Publication status | Published - 6 Mar 2023 |
MoE publication type | A1 Journal article-refereed |
Keywords
- Differential coupler
- Gain
- gain tuning
- low-noise amplifier
- millimeter-wave
- MMIC
- Noise figure
- phase shifter
- Phase shifters
- phased-array
- power amplifier
- Power amplifiers
- Radio frequency
- receiver
- Receivers
- transmitter
- Transmitters