3D processing on 6 in. high resistive SOI wafers

Fabrication of edgeless strip and pixel detectors

Simo Eränen, Juha Kalliopuska (Corresponding Author), Risto Orava, Nick van Remortel, Tuula Virolainen

Research output: Contribution to journalArticleScientificpeer-review

16 Citations (Scopus)

Abstract

An insight is given into the state-of-the-art 3D processing on 6 in. (150 mm) high resistivity silicon-on-insulator (SOI) wafers. The edgeless detector design offers some attractive properties for high-energy physics experiments and medical imaging studies, such as seamless tileability of the detectors with an inactive region width of about 10 μm. These detectors can be made very thin and the active edge avoids inhomogeneous electric fields and surface leakage currents.

The paper summarizes the fabrication of edgeless detectors and the issues faced in the 3D processing on 6 in. SOI wafers. The fabrication process employed highly doped polysilicon filling in order to implement the active edges of the detector. Several planarization and ICP-etching steps were required. The layout had microstrip detectors with a pitch of 50 μm and sizes of 5×5 cm2 and 1×1 cm2, and Medipix2 compatible 1.4×1.4 cm2 pixel detectors. Also several test structures were fabricated.

Electrical characterization of a 150-μm-thick edgeless diode showed low leakage currents, below 1 nA/cm2 at full depletion. The single-strip measurements showed leakage currents of about 10 pA/cm, regardless of the detector size. Low breakdown voltage of about 20 V was observed for several detectors. This might be caused by cracking of the detector edges following self-dicing. A simplified process flow for the fabrication of edgeless detectors is presented. The process is straightforward and fast because it excludes multiple ion coupled plasma (ICP)-etching steps, slow and wafer-damaging polysilicon filling and planarization steps. First images of the prototype are presented.

Original languageEnglish
Pages (from-to)85-88
JournalNuclear Instruments and Methods in Physics Research. Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
Volume607
Issue number1
DOIs
Publication statusPublished - 2009
MoE publication typeA1 Journal article-refereed

Fingerprint

strip
Pixels
pixels
insulators
wafers
Detectors
Fabrication
Silicon
fabrication
detectors
silicon
Processing
Leakage currents
leakage
Plasma etching
plasma etching
Polysilicon
High energy physics
Medical imaging
Ions

Keywords

  • Edgeless detector
  • Microstrip detector
  • Pixel detector
  • Silicon-on-insulator
  • Edge ion implantation

Cite this

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title = "3D processing on 6 in. high resistive SOI wafers: Fabrication of edgeless strip and pixel detectors",
abstract = "An insight is given into the state-of-the-art 3D processing on 6 in. (150 mm) high resistivity silicon-on-insulator (SOI) wafers. The edgeless detector design offers some attractive properties for high-energy physics experiments and medical imaging studies, such as seamless tileability of the detectors with an inactive region width of about 10 μm. These detectors can be made very thin and the active edge avoids inhomogeneous electric fields and surface leakage currents.The paper summarizes the fabrication of edgeless detectors and the issues faced in the 3D processing on 6 in. SOI wafers. The fabrication process employed highly doped polysilicon filling in order to implement the active edges of the detector. Several planarization and ICP-etching steps were required. The layout had microstrip detectors with a pitch of 50 μm and sizes of 5×5 cm2 and 1×1 cm2, and Medipix2 compatible 1.4×1.4 cm2 pixel detectors. Also several test structures were fabricated.Electrical characterization of a 150-μm-thick edgeless diode showed low leakage currents, below 1 nA/cm2 at full depletion. The single-strip measurements showed leakage currents of about 10 pA/cm, regardless of the detector size. Low breakdown voltage of about 20 V was observed for several detectors. This might be caused by cracking of the detector edges following self-dicing. A simplified process flow for the fabrication of edgeless detectors is presented. The process is straightforward and fast because it excludes multiple ion coupled plasma (ICP)-etching steps, slow and wafer-damaging polysilicon filling and planarization steps. First images of the prototype are presented.",
keywords = "Edgeless detector, Microstrip detector, Pixel detector, Silicon-on-insulator, Edge ion implantation",
author = "Simo Er{\"a}nen and Juha Kalliopuska and Risto Orava and {van Remortel}, Nick and Tuula Virolainen",
year = "2009",
doi = "10.1016/j.nima.2009.03.243",
language = "English",
volume = "607",
pages = "85--88",
journal = "Nuclear Instruments and Methods in Physics Research. Section A: Accelerators, Spectrometers, Detectors and Associated Equipment",
issn = "0168-9002",
publisher = "Elsevier",
number = "1",

}

3D processing on 6 in. high resistive SOI wafers : Fabrication of edgeless strip and pixel detectors. / Eränen, Simo; Kalliopuska, Juha (Corresponding Author); Orava, Risto; van Remortel, Nick; Virolainen, Tuula.

In: Nuclear Instruments and Methods in Physics Research. Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, Vol. 607, No. 1, 2009, p. 85-88.

Research output: Contribution to journalArticleScientificpeer-review

TY - JOUR

T1 - 3D processing on 6 in. high resistive SOI wafers

T2 - Fabrication of edgeless strip and pixel detectors

AU - Eränen, Simo

AU - Kalliopuska, Juha

AU - Orava, Risto

AU - van Remortel, Nick

AU - Virolainen, Tuula

PY - 2009

Y1 - 2009

N2 - An insight is given into the state-of-the-art 3D processing on 6 in. (150 mm) high resistivity silicon-on-insulator (SOI) wafers. The edgeless detector design offers some attractive properties for high-energy physics experiments and medical imaging studies, such as seamless tileability of the detectors with an inactive region width of about 10 μm. These detectors can be made very thin and the active edge avoids inhomogeneous electric fields and surface leakage currents.The paper summarizes the fabrication of edgeless detectors and the issues faced in the 3D processing on 6 in. SOI wafers. The fabrication process employed highly doped polysilicon filling in order to implement the active edges of the detector. Several planarization and ICP-etching steps were required. The layout had microstrip detectors with a pitch of 50 μm and sizes of 5×5 cm2 and 1×1 cm2, and Medipix2 compatible 1.4×1.4 cm2 pixel detectors. Also several test structures were fabricated.Electrical characterization of a 150-μm-thick edgeless diode showed low leakage currents, below 1 nA/cm2 at full depletion. The single-strip measurements showed leakage currents of about 10 pA/cm, regardless of the detector size. Low breakdown voltage of about 20 V was observed for several detectors. This might be caused by cracking of the detector edges following self-dicing. A simplified process flow for the fabrication of edgeless detectors is presented. The process is straightforward and fast because it excludes multiple ion coupled plasma (ICP)-etching steps, slow and wafer-damaging polysilicon filling and planarization steps. First images of the prototype are presented.

AB - An insight is given into the state-of-the-art 3D processing on 6 in. (150 mm) high resistivity silicon-on-insulator (SOI) wafers. The edgeless detector design offers some attractive properties for high-energy physics experiments and medical imaging studies, such as seamless tileability of the detectors with an inactive region width of about 10 μm. These detectors can be made very thin and the active edge avoids inhomogeneous electric fields and surface leakage currents.The paper summarizes the fabrication of edgeless detectors and the issues faced in the 3D processing on 6 in. SOI wafers. The fabrication process employed highly doped polysilicon filling in order to implement the active edges of the detector. Several planarization and ICP-etching steps were required. The layout had microstrip detectors with a pitch of 50 μm and sizes of 5×5 cm2 and 1×1 cm2, and Medipix2 compatible 1.4×1.4 cm2 pixel detectors. Also several test structures were fabricated.Electrical characterization of a 150-μm-thick edgeless diode showed low leakage currents, below 1 nA/cm2 at full depletion. The single-strip measurements showed leakage currents of about 10 pA/cm, regardless of the detector size. Low breakdown voltage of about 20 V was observed for several detectors. This might be caused by cracking of the detector edges following self-dicing. A simplified process flow for the fabrication of edgeless detectors is presented. The process is straightforward and fast because it excludes multiple ion coupled plasma (ICP)-etching steps, slow and wafer-damaging polysilicon filling and planarization steps. First images of the prototype are presented.

KW - Edgeless detector

KW - Microstrip detector

KW - Pixel detector

KW - Silicon-on-insulator

KW - Edge ion implantation

U2 - 10.1016/j.nima.2009.03.243

DO - 10.1016/j.nima.2009.03.243

M3 - Article

VL - 607

SP - 85

EP - 88

JO - Nuclear Instruments and Methods in Physics Research. Section A: Accelerators, Spectrometers, Detectors and Associated Equipment

JF - Nuclear Instruments and Methods in Physics Research. Section A: Accelerators, Spectrometers, Detectors and Associated Equipment

SN - 0168-9002

IS - 1

ER -