8x8 Multiplier Based on Adiabatic Static Logic

Jouko Marjonen, Markku Åberg

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientific


    This paper continues presenting measurement results of a larger digital system based on the adiabatic static logic (ASL). The fundamental purpose of the research have been too investigate the useability of the ASL gates on a larger system as a possible solution to the power consumption problem existing in many digital CMOS circuits; an additional purpose of the present study have been to prove that a double clocked power source increases the power efficiency of the ASL system over the sigle clocked version. This time, a 8x8 multiplier was used as a demonstration.
    Original languageEnglish
    Title of host publicationProceedings of 21st Norchip Conference
    PublisherTechnoData A/S
    ISBN (Print)87-9826637-5-7
    Publication statusPublished - 2003
    MoE publication typeB3 Non-refereed article in conference proceedings
    Event21st Norchip Conference, NORCHIP 2003 - Riga, Latvia
    Duration: 10 Nov 200311 Nov 2003


    Conference21st Norchip Conference, NORCHIP 2003


    • Logic
    • low power
    • Adiabatic
    • recycling
    • system


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