Abstract
This paper continues presenting measurement results of a larger digital system based on the adiabatic static logic (ASL). The fundamental purpose of the research have been too investigate the useability of the ASL gates on a larger system as a possible solution to the power consumption problem existing in many digital CMOS circuits; an additional purpose of the present study have been to prove that a double clocked power source increases the power efficiency of the ASL system over the sigle clocked version. This time, a 8x8 multiplier was used as a demonstration.
Original language | English |
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Title of host publication | Proceedings of 21st Norchip Conference |
Publisher | TechnoData A/S |
Pages | 187-190 |
ISBN (Print) | 87-9826637-5-7 |
Publication status | Published - 2003 |
MoE publication type | B3 Non-refereed article in conference proceedings |
Event | 21st Norchip Conference, NORCHIP 2003 - Riga, Latvia Duration: 10 Nov 2003 → 11 Nov 2003 |
Conference
Conference | 21st Norchip Conference, NORCHIP 2003 |
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Country/Territory | Latvia |
City | Riga |
Period | 10/11/03 → 11/11/03 |
Keywords
- Logic
- low power
- Adiabatic
- recycling
- system