Abstract
Prescalers based on dynamic CMOS logic using minimum gate delays have been demonstrated as a front end for the RF synthesizers in the 1-GHz region. A speed-power product optimization method for the complementary dynamic logic has been developed and the gradual layout technique has been applied to increase the circuit yield. It is shown that it is possible to reach a 1-GHz input frequency in prescalers based on CMOS and dynamic logic only by scaling the effective channel length of the MOS transistors down to 1.1 μm.
Original language | English |
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Title of host publication | 1988 IEEE International Symposium on Circuits and Systems, ISCAS 88 |
Place of Publication | Espoo |
Publisher | IEEE Institute of Electrical and Electronic Engineers |
Pages | 377-380 |
Volume | 2 |
DOIs | |
Publication status | Published - 1988 |
MoE publication type | A4 Article in a conference publication |
Event | 1988 IEEE International Symposium on Circuits and Systems, ISCAS 88 - Espoo, Finland Duration: 7 Jul 1988 → 9 Jul 1988 |
Conference
Conference | 1988 IEEE International Symposium on Circuits and Systems, ISCAS 88 |
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Country/Territory | Finland |
City | Espoo |
Period | 7/07/88 → 9/07/88 |