A 10-bit, 1.8-GS/s time-interleaved pipeline ADC

V. Hakkarainen, Arto Rantala, M. Aho, J. Riikonen, David Gomes-Martins, Markku Åberg, K. Halonen

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    3 Citations (Scopus)

    Abstract

    In this paper, a 10-bit, 1.8-GS/s time-interleaved analog-to-digital converter (ADC) is presented. The ADC employs 24 parallel 10-bit pipeline ADCs to reach the conversion rate of 1.8GS/s. Sampling clocks are generated by a delay-locked loop (DLL), which includes a calibration of timing skew.
    Offset and gain error are calibrated in order to overcome the effects of device mismatch within a channel ADC.
    The ADC, implemented with a 0.35-μm BiCMOS, achieves an effective number of bits (ENOB) of 7.19 bits with a 764-MHz input while consuming 3.5W of power.
    Original languageEnglish
    Title of host publicationProceedings of the 14th IEEE International Conference on Electronics, Circuits, and Systems
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Pages673-676
    ISBN (Print)978-1-4244-1377-5, 978-1-4244-1378-2
    DOIs
    Publication statusPublished - 2007
    MoE publication typeA4 Article in a conference publication
    Event14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Morocco
    Duration: 11 Dec 200714 Dec 2007

    Conference

    Conference14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
    CountryMorocco
    CityMarrakech
    Period11/12/0714/12/07

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  • Cite this

    Hakkarainen, V., Rantala, A., Aho, M., Riikonen, J., Gomes-Martins, D., Åberg, M., & Halonen, K. (2007). A 10-bit, 1.8-GS/s time-interleaved pipeline ADC. In Proceedings of the 14th IEEE International Conference on Electronics, Circuits, and Systems (pp. 673-676). IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.1109/ICECS.2007.4511081