A 10-bit, 1.8-GS/s time-interleaved pipeline ADC

V. Hakkarainen; Arto Rantala; M. Aho; J. Riikonen; David Gomes-Martins; Markku Åberg; K. Halonen

doi:10.1109/ICECS.2007.4511081

A 10-bit, 1.8-GS/s time-interleaved pipeline ADC

V. Hakkarainen, Arto Rantala, M. Aho, J. Riikonen, David Gomes-Martins, Markku Åberg, K. Halonen

Helsinki University of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

3 Citations (Scopus)

Abstract

In this paper, a 10-bit, 1.8-GS/s time-interleaved analog-to-digital converter (ADC) is presented. The ADC employs 24 parallel 10-bit pipeline ADCs to reach the conversion rate of 1.8GS/s. Sampling clocks are generated by a delay-locked loop (DLL), which includes a calibration of timing skew.
Offset and gain error are calibrated in order to overcome the effects of device mismatch within a channel ADC.
The ADC, implemented with a 0.35-μm BiCMOS, achieves an effective number of bits (ENOB) of 7.19 bits with a 764-MHz input while consuming 3.5W of power.

Original language	English
Title of host publication	Proceedings of the 14th IEEE International Conference on Electronics, Circuits, and Systems
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	673-676
ISBN (Print)	978-1-4244-1377-5, 978-1-4244-1378-2
DOIs	https://doi.org/10.1109/ICECS.2007.4511081
Publication status	Published - 2007
MoE publication type	A4 Article in a conference publication
Event	14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Morocco Duration: 11 Dec 2007 → 14 Dec 2007

Conference

Conference	14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
Country/Territory	Morocco
City	Marrakech
Period	11/12/07 → 14/12/07

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10.1109/ICECS.2007.4511081

Cite this

@inproceedings{c3727106543f4c06a3861494ff58172a,

title = "A 10-bit, 1.8-GS/s time-interleaved pipeline ADC",

abstract = "In this paper, a 10-bit, 1.8-GS/s time-interleaved analog-to-digital converter (ADC) is presented. The ADC employs 24 parallel 10-bit pipeline ADCs to reach the conversion rate of 1.8GS/s. Sampling clocks are generated by a delay-locked loop (DLL), which includes a calibration of timing skew. Offset and gain error are calibrated in order to overcome the effects of device mismatch within a channel ADC. The ADC, implemented with a 0.35-μm BiCMOS, achieves an effective number of bits (ENOB) of 7.19 bits with a 764-MHz input while consuming 3.5W of power.",

author = "V. Hakkarainen and Arto Rantala and M. Aho and J. Riikonen and David Gomes-Martins and Markku {\AA}berg and K. Halonen",

year = "2007",

doi = "10.1109/ICECS.2007.4511081",

language = "English",

isbn = "978-1-4244-1377-5",

pages = "673--676",

booktitle = "Proceedings of the 14th IEEE International Conference on Electronics, Circuits, and Systems",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

note = "14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 ; Conference date: 11-12-2007 Through 14-12-2007",

}

Hakkarainen, V, Rantala, A, Aho, M, Riikonen, J, Gomes-Martins, D, Åberg, M & Halonen, K 2007, A 10-bit, 1.8-GS/s time-interleaved pipeline ADC. in Proceedings of the 14th IEEE International Conference on Electronics, Circuits, and Systems. IEEE Institute of Electrical and Electronic Engineers, pp. 673-676, 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007, Marrakech, Morocco, 11/12/07. https://doi.org/10.1109/ICECS.2007.4511081

A 10-bit, 1.8-GS/s time-interleaved pipeline ADC. / Hakkarainen, V.; Rantala, Arto; Aho, M. et al.
Proceedings of the 14th IEEE International Conference on Electronics, Circuits, and Systems. IEEE Institute of Electrical and Electronic Engineers, 2007. p. 673-676.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

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T1 - A 10-bit, 1.8-GS/s time-interleaved pipeline ADC

AU - Hakkarainen, V.

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AU - Gomes-Martins, David

AU - Åberg, Markku

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N2 - In this paper, a 10-bit, 1.8-GS/s time-interleaved analog-to-digital converter (ADC) is presented. The ADC employs 24 parallel 10-bit pipeline ADCs to reach the conversion rate of 1.8GS/s. Sampling clocks are generated by a delay-locked loop (DLL), which includes a calibration of timing skew. Offset and gain error are calibrated in order to overcome the effects of device mismatch within a channel ADC. The ADC, implemented with a 0.35-μm BiCMOS, achieves an effective number of bits (ENOB) of 7.19 bits with a 764-MHz input while consuming 3.5W of power.

AB - In this paper, a 10-bit, 1.8-GS/s time-interleaved analog-to-digital converter (ADC) is presented. The ADC employs 24 parallel 10-bit pipeline ADCs to reach the conversion rate of 1.8GS/s. Sampling clocks are generated by a delay-locked loop (DLL), which includes a calibration of timing skew. Offset and gain error are calibrated in order to overcome the effects of device mismatch within a channel ADC. The ADC, implemented with a 0.35-μm BiCMOS, achieves an effective number of bits (ENOB) of 7.19 bits with a 764-MHz input while consuming 3.5W of power.

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DO - 10.1109/ICECS.2007.4511081

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SN - 978-1-4244-1378-2

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BT - Proceedings of the 14th IEEE International Conference on Electronics, Circuits, and Systems

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007

Y2 - 11 December 2007 through 14 December 2007

ER -

A 10-bit, 1.8-GS/s time-interleaved pipeline ADC

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