A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

M. Hiienkari, J. Teittinen, L. Koskinen, M. Turnquist, M. Kaltiokallio, J. Mäkipää, A. Rantala, M. Sopanen

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

8 Citations (Scopus)

Abstract

The increased performance from technology scaling makes it feasible to operate digital circuits at ultra-low voltages without the significant performance limitation of earlier process generations. The theoretical minimum energy point resides in near-threshold voltages in current processes, but device and environment variations make it a challenge to operate the circuits reliably. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS employing timing-error prevention with clock stretching to enable it to operate with minimal safety margins while maximizing energy efficiency. Measurements show 3.15pJ/cyc energy consumption at 400mV/2.4MHz, which corresponds to 39% energy savings and 83% EDP reduction compared to operation based on static signoff timing.
Original languageEnglish
Title of host publicationProceedings of the IEEE 2014 Custom Integrated Circuits Conference
PublisherIEEE Institute of Electrical and Electronic Engineers
Pages1-4
ISBN (Print)1-4799-3286-8, 978-1-4799-3286-3
DOIs
Publication statusPublished - 2014
MoE publication typeA4 Article in a conference publication
EventIEEE 2014 Custom Integrated Circuits Conference, CICC, 36th Annual Custom Integrated Circuits Conference - San Jose, United States
Duration: 15 Sep 201417 Sep 2014

Conference

ConferenceIEEE 2014 Custom Integrated Circuits Conference, CICC, 36th Annual Custom Integrated Circuits Conference
Abbreviated titleCICC 2014
CountryUnited States
CitySan Jose
Period15/09/1417/09/14

Keywords

  • adaptation models
  • CMOS integrated circuits
  • central processing unit
  • clocks
  • latches
  • pipelines
  • timing

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