A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

Markus Hiienkari; Jukka Teittinen; Lauri Koskinen; Matthew Turnquist; Mikko Kaltiokallio; Jani Mäkipää; Arto Rantala; Matti Sopanen

doi:10.1109/CICC.2014.6946095

A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

Markus Hiienkari
, Jukka Teittinen
, Lauri Koskinen
, Matthew Turnquist
, Mikko Kaltiokallio
, Jani Mäkipää
, Arto Rantala
, Matti Sopanen

VTT Technical Research Centre of Finland

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

11 Citations (Scopus)

Abstract

The increased performance from technology scaling makes it feasible to operate digital circuits at ultra-low voltages without the significant performance limitation of earlier process generations. The theoretical minimum energy point resides in near-threshold voltages in current processes, but device and environment variations make it a challenge to operate the circuits reliably. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS employing timing-error prevention with clock stretching to enable it to operate with minimal safety margins while maximizing energy efficiency. Measurements show 3.15pJ/cyc energy consumption at 400mV/2.4MHz, which corresponds to 39% energy savings and 83% EDP reduction compared to operation based on static signoff timing.

Original language	English
Title of host publication	Proceedings of the IEEE 2014 Custom Integrated Circuits Conference
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	1-4
ISBN (Print)	978-1-4799-3286-3
DOIs	https://doi.org/10.1109/CICC.2014.6946095
Publication status	Published - 2014
MoE publication type	A4 Article in a conference publication
Event	IEEE 2014 Custom Integrated Circuits Conference, CICC, 36th Annual Custom Integrated Circuits Conference - San Jose, United States Duration: 15 Sept 2014 → 17 Sept 2014

Publication series

Series	Proceedings of the Custom Integrated Circuits Conference
ISSN	0886-5930

Conference

Conference	IEEE 2014 Custom Integrated Circuits Conference, CICC, 36th Annual Custom Integrated Circuits Conference
Abbreviated title	CICC 2014
Country/Territory	United States
City	San Jose
Period	15/09/14 → 17/09/14

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

adaptation models
CMOS integrated circuits
central processing unit
clocks
latches
pipelines
timing

Access to Document

10.1109/CICC.2014.6946095

Cite this

Hiienkari, M., Teittinen, J., Koskinen, L., Turnquist, M., Kaltiokallio, M., Mäkipää, J., Rantala, A., & Sopanen, M. (2014). A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference (pp. 1-4). IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.1109/CICC.2014.6946095

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title = "A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS",

abstract = "The increased performance from technology scaling makes it feasible to operate digital circuits at ultra-low voltages without the significant performance limitation of earlier process generations. The theoretical minimum energy point resides in near-threshold voltages in current processes, but device and environment variations make it a challenge to operate the circuits reliably. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS employing timing-error prevention with clock stretching to enable it to operate with minimal safety margins while maximizing energy efficiency. Measurements show 3.15pJ/cyc energy consumption at 400mV/2.4MHz, which corresponds to 39\% energy savings and 83\% EDP reduction compared to operation based on static signoff timing.",

keywords = "adaptation models, CMOS integrated circuits, central processing unit, clocks, latches, pipelines, timing",

author = "Markus Hiienkari and Jukka Teittinen and Lauri Koskinen and Matthew Turnquist and Mikko Kaltiokallio and Jani M{\"a}kip{\"a}{\"a} and Arto Rantala and Matti Sopanen",

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Hiienkari, M, Teittinen, J, Koskinen, L, Turnquist, M, Kaltiokallio, M, Mäkipää, J, Rantala, A & Sopanen, M 2014, A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS. in Proceedings of the IEEE 2014 Custom Integrated Circuits Conference. IEEE Institute of Electrical and Electronic Engineers, Proceedings of the Custom Integrated Circuits Conference, pp. 1-4, IEEE 2014 Custom Integrated Circuits Conference, CICC, 36th Annual Custom Integrated Circuits Conference, San Jose, United States, 15/09/14. https://doi.org/10.1109/CICC.2014.6946095

A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS. / Hiienkari, Markus; Teittinen, Jukka; Koskinen, Lauri et al.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference. IEEE Institute of Electrical and Electronic Engineers, 2014. p. 1-4 (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

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AU - Turnquist, Matthew

AU - Kaltiokallio, Mikko

AU - Mäkipää, Jani

AU - Rantala, Arto

AU - Sopanen, Matti

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AB - The increased performance from technology scaling makes it feasible to operate digital circuits at ultra-low voltages without the significant performance limitation of earlier process generations. The theoretical minimum energy point resides in near-threshold voltages in current processes, but device and environment variations make it a challenge to operate the circuits reliably. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS employing timing-error prevention with clock stretching to enable it to operate with minimal safety margins while maximizing energy efficiency. Measurements show 3.15pJ/cyc energy consumption at 400mV/2.4MHz, which corresponds to 39% energy savings and 83% EDP reduction compared to operation based on static signoff timing.

KW - adaptation models

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KW - central processing unit

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KW - latches

KW - pipelines

KW - timing

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Hiienkari M, Teittinen J, Koskinen L, Turnquist M, Kaltiokallio M, Mäkipää J et al. A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference. IEEE Institute of Electrical and Electronic Engineers. 2014. p. 1-4. (Proceedings of the Custom Integrated Circuits Conference). doi: 10.1109/CICC.2014.6946095

A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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