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A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS
M. Hiienkari, J. Teittinen, L. Koskinen, M. Turnquist, M. Kaltiokallio, J. Mäkipää, A. Rantala, M. Sopanen
Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review
8
Citations
(Scopus)