A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

Markus Hiienkari, Jukka Teittinen, Lauri Koskinen, Matthew Turnquist, Mikko Kaltiokallio, Jani Mäkipää, Arto Rantala, Matti Sopanen

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

10 Citations (Scopus)

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