A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

Keyphrases

• 28 Nm CMOS 100%
• 32-bit 100%
• Adaptive Clocking 100%
• ASIC Implementation 50%
• Clock Stretching 50%
• Device Variations 50%
• Digital Circuits 50%
• Energy Consumption 50%
• Energy Efficiency 50%
• Energy Saving 50%
• Environmental Variability 50%
• Error Prevention 100%
• Increased Performance 50%
• Minimum Energy Point 50%
• Near-threshold Voltage 50%
• Operation-based 50%
• Performance Limitation 50%
• Process Generation 50%
• RISC Processor 100%
• Safety Margin 50%
• Technology Scaling 50%
• Timing Error 100%
• Ultra-low Voltage 50%

INIS

• comparative evaluations 50%
• devices 50%
• digital circuits 50%
• energy 100%
• energy consumption 50%
• energy efficiency 50%
• environment 50%
• errors 100%
• implementation 50%
• operation 50%
• performance 100%
• reduction 50%
• safety margins 50%
• scaling 50%
• variations 50%
• voltage 100%

Engineering

• Application Specific Integrated Circuit 50%
• Digital Circuits 50%
• Energy Conservation 100%
• Energy Efficiency 50%
• Energy Engineering 50%
• Safety Margin 50%