A comprehensive study of carrier velocity modulation in DGSOI transistors

C. Sampedro (Corresponding Author), F. Gamiz, A. Godoy, Jouni Ahopelto, Mika Prunnila

Research output: Contribution to journalArticleScientificpeer-review

2 Citations (Scopus)

Abstract

Velocity modulation transistors (VMT) are proposed as a way to explode short transit time between two adjacent channels with different transport properties in order to obtain a fast switch. Originally proposed for III–V heterostructures, a Monte Carlo study of silicon-based VMTs is presented in this work showing that surface roughness in double-gate silicon-on-insulator devices can be used as a mobility degradation mechanism to obtain current ratios higher than 30 and therefore feasible devices. Transient simulations have been also carried out obtaining sub-picosecond switch times for 0.1 μm gate length. Switch time limitations are also discussed including both intrinsic and extrinsic factors.
Original languageEnglish
Pages (from-to)1504 - 1509
Number of pages6
JournalSolid-State Electronics
Volume49
Issue number9
DOIs
Publication statusPublished - 2005
MoE publication typeA1 Journal article-refereed

Fingerprint

Time switches
velocity modulation
Silicon
Transistors
transistors
switches
Modulation
Transport properties
Heterojunctions
Surface roughness
Switches
silicon
transit time
Degradation
surface roughness
transport properties
insulators
degradation
simulation

Keywords

  • velocity modulation transistor
  • VMT
  • double gate SOI
  • SOI
  • silicon-on-insulator
  • monte carlo

Cite this

@article{9e986a75a9e841bbbf0ab29f18bb0343,
title = "A comprehensive study of carrier velocity modulation in DGSOI transistors",
abstract = "Velocity modulation transistors (VMT) are proposed as a way to explode short transit time between two adjacent channels with different transport properties in order to obtain a fast switch. Originally proposed for III–V heterostructures, a Monte Carlo study of silicon-based VMTs is presented in this work showing that surface roughness in double-gate silicon-on-insulator devices can be used as a mobility degradation mechanism to obtain current ratios higher than 30 and therefore feasible devices. Transient simulations have been also carried out obtaining sub-picosecond switch times for 0.1 μm gate length. Switch time limitations are also discussed including both intrinsic and extrinsic factors.",
keywords = "velocity modulation transistor, VMT, double gate SOI, SOI, silicon-on-insulator, monte carlo",
author = "C. Sampedro and F. Gamiz and A. Godoy and Jouni Ahopelto and Mika Prunnila",
year = "2005",
doi = "10.1016/j.sse.2005.07.014",
language = "English",
volume = "49",
pages = "1504 -- 1509",
journal = "Solid-State Electronics",
issn = "0038-1101",
publisher = "Elsevier",
number = "9",

}

A comprehensive study of carrier velocity modulation in DGSOI transistors. / Sampedro, C. (Corresponding Author); Gamiz, F.; Godoy, A.; Ahopelto, Jouni; Prunnila, Mika.

In: Solid-State Electronics, Vol. 49, No. 9, 2005, p. 1504 - 1509.

Research output: Contribution to journalArticleScientificpeer-review

TY - JOUR

T1 - A comprehensive study of carrier velocity modulation in DGSOI transistors

AU - Sampedro, C.

AU - Gamiz, F.

AU - Godoy, A.

AU - Ahopelto, Jouni

AU - Prunnila, Mika

PY - 2005

Y1 - 2005

N2 - Velocity modulation transistors (VMT) are proposed as a way to explode short transit time between two adjacent channels with different transport properties in order to obtain a fast switch. Originally proposed for III–V heterostructures, a Monte Carlo study of silicon-based VMTs is presented in this work showing that surface roughness in double-gate silicon-on-insulator devices can be used as a mobility degradation mechanism to obtain current ratios higher than 30 and therefore feasible devices. Transient simulations have been also carried out obtaining sub-picosecond switch times for 0.1 μm gate length. Switch time limitations are also discussed including both intrinsic and extrinsic factors.

AB - Velocity modulation transistors (VMT) are proposed as a way to explode short transit time between two adjacent channels with different transport properties in order to obtain a fast switch. Originally proposed for III–V heterostructures, a Monte Carlo study of silicon-based VMTs is presented in this work showing that surface roughness in double-gate silicon-on-insulator devices can be used as a mobility degradation mechanism to obtain current ratios higher than 30 and therefore feasible devices. Transient simulations have been also carried out obtaining sub-picosecond switch times for 0.1 μm gate length. Switch time limitations are also discussed including both intrinsic and extrinsic factors.

KW - velocity modulation transistor

KW - VMT

KW - double gate SOI

KW - SOI

KW - silicon-on-insulator

KW - monte carlo

U2 - 10.1016/j.sse.2005.07.014

DO - 10.1016/j.sse.2005.07.014

M3 - Article

VL - 49

SP - 1504

EP - 1509

JO - Solid-State Electronics

JF - Solid-State Electronics

SN - 0038-1101

IS - 9

ER -