A comprehensive study of carrier velocity modulation in DGSOI transistors

C. Sampedro; F. Gamiz; A. Godoy; Jouni Ahopelto; Mika Prunnila

doi:10.1016/j.sse.2005.07.014

A comprehensive study of carrier velocity modulation in DGSOI transistors

C. Sampedro (Corresponding Author), F. Gamiz, A. Godoy, Jouni Ahopelto, Mika Prunnila

University of Granada

Research output: Contribution to journal › Article › Scientific › peer-review

2 Citations (Scopus)

Abstract

Velocity modulation transistors (VMT) are proposed as a way to explode short transit time between two adjacent channels with different transport properties in order to obtain a fast switch. Originally proposed for III–V heterostructures, a Monte Carlo study of silicon-based VMTs is presented in this work showing that surface roughness in double-gate silicon-on-insulator devices can be used as a mobility degradation mechanism to obtain current ratios higher than 30 and therefore feasible devices. Transient simulations have been also carried out obtaining sub-picosecond switch times for 0.1 μm gate length. Switch time limitations are also discussed including both intrinsic and extrinsic factors.

Original language	English
Pages (from-to)	1504 - 1509
Number of pages	6
Journal	Solid-State Electronics
Volume	49
Issue number	9
DOIs	https://doi.org/10.1016/j.sse.2005.07.014
Publication status	Published - 2005
MoE publication type	A1 Journal article-refereed
Event	1st Workshop of the Thematic Network on Silicon On Insulator Technology, Devices and Circuits, EUROSOI 2005 - Granada, Spain Duration: 19 Jan 2005 → 21 Jan 2005

Keywords

velocity modulation transistor
VMT
double gate SOI
SOI
silicon-on-insulator
monte carlo

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10.1016/j.sse.2005.07.014

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title = "A comprehensive study of carrier velocity modulation in DGSOI transistors",

abstract = "Velocity modulation transistors (VMT) are proposed as a way to explode short transit time between two adjacent channels with different transport properties in order to obtain a fast switch. Originally proposed for III–V heterostructures, a Monte Carlo study of silicon-based VMTs is presented in this work showing that surface roughness in double-gate silicon-on-insulator devices can be used as a mobility degradation mechanism to obtain current ratios higher than 30 and therefore feasible devices. Transient simulations have been also carried out obtaining sub-picosecond switch times for 0.1 μm gate length. Switch time limitations are also discussed including both intrinsic and extrinsic factors.",

keywords = "velocity modulation transistor, VMT, double gate SOI, SOI, silicon-on-insulator, monte carlo",

author = "C. Sampedro and F. Gamiz and A. Godoy and Jouni Ahopelto and Mika Prunnila",

year = "2005",

doi = "10.1016/j.sse.2005.07.014",

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journal = "Solid-State Electronics",

issn = "0038-1101",

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note = "1st Workshop of the Thematic Network on Silicon On Insulator Technology, Devices and Circuits, EUROSOI 2005 ; Conference date: 19-01-2005 Through 21-01-2005",

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TY - JOUR

T1 - A comprehensive study of carrier velocity modulation in DGSOI transistors

AU - Sampedro, C.

AU - Gamiz, F.

AU - Godoy, A.

AU - Ahopelto, Jouni

AU - Prunnila, Mika

PY - 2005

Y1 - 2005

N2 - Velocity modulation transistors (VMT) are proposed as a way to explode short transit time between two adjacent channels with different transport properties in order to obtain a fast switch. Originally proposed for III–V heterostructures, a Monte Carlo study of silicon-based VMTs is presented in this work showing that surface roughness in double-gate silicon-on-insulator devices can be used as a mobility degradation mechanism to obtain current ratios higher than 30 and therefore feasible devices. Transient simulations have been also carried out obtaining sub-picosecond switch times for 0.1 μm gate length. Switch time limitations are also discussed including both intrinsic and extrinsic factors.

AB - Velocity modulation transistors (VMT) are proposed as a way to explode short transit time between two adjacent channels with different transport properties in order to obtain a fast switch. Originally proposed for III–V heterostructures, a Monte Carlo study of silicon-based VMTs is presented in this work showing that surface roughness in double-gate silicon-on-insulator devices can be used as a mobility degradation mechanism to obtain current ratios higher than 30 and therefore feasible devices. Transient simulations have been also carried out obtaining sub-picosecond switch times for 0.1 μm gate length. Switch time limitations are also discussed including both intrinsic and extrinsic factors.

KW - velocity modulation transistor

KW - VMT

KW - double gate SOI

KW - SOI

KW - silicon-on-insulator

KW - monte carlo

U2 - 10.1016/j.sse.2005.07.014

DO - 10.1016/j.sse.2005.07.014

M3 - Article

SN - 0038-1101

VL - 49

SP - 1504

EP - 1509

JO - Solid-State Electronics

JF - Solid-State Electronics

IS - 9

T2 - 1st Workshop of the Thematic Network on Silicon On Insulator Technology, Devices and Circuits, EUROSOI 2005

Y2 - 19 January 2005 through 21 January 2005

ER -

A comprehensive study of carrier velocity modulation in DGSOI transistors

Abstract

Keywords

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