A D-Band 16-Element Phased-Array Transceiver in 55-nm BiCMOS

A 16-element 140–160-GHz phased array transceiver is reported. The chipset is fabricated using STMicroelectronics’ 55-nm SiGe BiCMOS process. Five different chips are implemented: a 4-channel transmitter with a maximum gain per channel of 15 dB and 0-dBm saturated output power; a 4-channel receiver with a maximum gain of 8 dB, a − 10.4-dBm input 1-dB compression point (IP 1dB ), and a minimum noise figure (NF) of 15.6 dB per channel; a 0–1-GHz to 140–160-GHz I/Q up-converter with integrated frequency doubler, exhibiting a − 13.5-dB conversion gain (CG) and − 6-dBm output 1-dB compression point using a 70–80-GHz local oscillator (LO); a 140–160-GHz to 0–1-GHz I/Q down-converter with integrated frequency doubler, exhibiting a CG of 0 dB and IP 1dB of 0 dBm using a 70–80-GHz LO and an 11.67–13.33-GHz to 70–80-GHz x6 frequency multiplier for the LO, delivering 5.6-dBm maximum output power. The chips are assembled together with 16 cavity-backed aperture-coupled patch antennas using a high-performance and low-cost commercial PCB, supported over a heat sink. The main challenges encountered during the integration of the proposed system are also discussed. The complete system is used to build a wireless radio link in the laboratory, demonstrating 2-D beam steering in a range of ± 30 ∘ .