A DLL based clock generator for a high speed time-interleaved A/D-converter

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientific


    This paper presents a clock generator circuit for a high speed analog-to-digital converter (ADC). A time interleaved ADC requires an accurate clocking for the converter fingers. The target ADC has 24 interleadved fingers each running at speed of 83 Ms/s which corresponds to equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide mulpiple clock signals for the converter. DLL clock generator has been implemented with 0.35 mm SiGe process by AMS and it occupies 0.66 mm silicon area.
    Original languageEnglish
    Title of host publicationProcedings 21st Norchip Conference
    PublisherTechnoData A/S
    ISBN (Print)87-9826637-5-7
    Publication statusPublished - 2003
    MoE publication typeB3 Non-refereed article in conference proceedings
    Event21st Norchip Conference, NORCHIP 2003 - Riga, Latvia
    Duration: 10 Nov 200311 Nov 2003


    Conference21st Norchip Conference, NORCHIP 2003


    • DLL
    • A/D-converter


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