A DLL based clock generator for a high speed time-interleaved A/D-converter

Arto Rantala; David Gomes Martins; Markku Åberg

A DLL based clock generator for a high speed time-interleaved A/D-converter

Arto Rantala, David Gomes Martins, Markku Åberg

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific

Abstract

This paper presents a clock generator circuit for a high speed analog-to-digital converter (ADC). A time interleaved ADC requires an accurate clocking for the converter fingers. The target ADC has 24 interleadved fingers each running at speed of 83 Ms/s which corresponds to equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide mulpiple clock signals for the converter. DLL clock generator has been implemented with 0.35 mm SiGe process by AMS and it occupies 0.66 mm silicon area.

Original language	English
Title of host publication	Procedings 21st Norchip Conference
Publisher	TechnoData A/S
Pages	125-128
ISBN (Print)	87-9826637-5-7
Publication status	Published - 2003
MoE publication type	B3 Non-refereed article in conference proceedings
Event	21st Norchip Conference, NORCHIP 2003 - Riga, Latvia Duration: 10 Nov 2003 → 11 Nov 2003

Conference

Conference	21st Norchip Conference, NORCHIP 2003
Country/Territory	Latvia
City	Riga
Period	10/11/03 → 11/11/03

Keywords

DLL
A/D-converter

Cite this

@inproceedings{2867c7a444a7446da8698199232e6a25,

title = "A DLL based clock generator for a high speed time-interleaved A/D-converter",

abstract = "This paper presents a clock generator circuit for a high speed analog-to-digital converter (ADC). A time interleaved ADC requires an accurate clocking for the converter fingers. The target ADC has 24 interleadved fingers each running at speed of 83 Ms/s which corresponds to equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide mulpiple clock signals for the converter. DLL clock generator has been implemented with 0.35 mm SiGe process by AMS and it occupies 0.66 mm silicon area.",

keywords = "DLL, A/D-converter",

author = "Arto Rantala and {Gomes Martins}, David and Markku {\AA}berg",

note = "Project code: t2su00415; 21st Norchip Conference, NORCHIP 2003 ; Conference date: 10-11-2003 Through 11-11-2003",

year = "2003",

language = "English",

isbn = "87-9826637-5-7",

pages = "125--128",

booktitle = "Procedings 21st Norchip Conference",

publisher = "TechnoData A/S",

address = "Denmark",

}

TY - GEN

T1 - A DLL based clock generator for a high speed time-interleaved A/D-converter

AU - Rantala, Arto

AU - Gomes Martins, David

AU - Åberg, Markku

N1 - Project code: t2su00415

PY - 2003

Y1 - 2003

N2 - This paper presents a clock generator circuit for a high speed analog-to-digital converter (ADC). A time interleaved ADC requires an accurate clocking for the converter fingers. The target ADC has 24 interleadved fingers each running at speed of 83 Ms/s which corresponds to equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide mulpiple clock signals for the converter. DLL clock generator has been implemented with 0.35 mm SiGe process by AMS and it occupies 0.66 mm silicon area.

AB - This paper presents a clock generator circuit for a high speed analog-to-digital converter (ADC). A time interleaved ADC requires an accurate clocking for the converter fingers. The target ADC has 24 interleadved fingers each running at speed of 83 Ms/s which corresponds to equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide mulpiple clock signals for the converter. DLL clock generator has been implemented with 0.35 mm SiGe process by AMS and it occupies 0.66 mm silicon area.

KW - DLL

KW - A/D-converter

M3 - Conference article in proceedings

SN - 87-9826637-5-7

SP - 125

EP - 128

BT - Procedings 21st Norchip Conference

PB - TechnoData A/S

T2 - 21st Norchip Conference, NORCHIP 2003

Y2 - 10 November 2003 through 11 November 2003

ER -

A DLL based clock generator for a high speed time-interleaved A/D-converter

Abstract

Conference

Keywords

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