This paper presents a clock generator circuit for a high speed analog-to-digital converter (ADC). A time interleaved ADC requires an accurate clocking for the converter fingers. The target ADC has 24 interleadved fingers each running at speed of 83 Ms/s which corresponds to equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide mulpiple clock signals for the converter. DLL clock generator has been implemented with 0.35 mm SiGe process by AMS and it occupies 0.66 mm silicon area.
|Title of host publication||Procedings 21st Norchip Conference|
|Publication status||Published - 2003|
|MoE publication type||B3 Non-refereed article in conference proceedings|
|Event||21st Norchip Conference, NORCHIP 2003 - Riga, Latvia|
Duration: 10 Nov 2003 → 11 Nov 2003
|Conference||21st Norchip Conference, NORCHIP 2003|
|Period||10/11/03 → 11/11/03|