A DLL clock generator for a high speed A/D converter with 1 ps jitter and skew calibrator with 1 ps accuracy in 0.35 μm CMOS

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    This paper presents a clock generator circuit for a high speed analog-to-digital converter (ADC). A time interleaved ADC requires an accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at speed of 166 MS/s which corresponds to equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 /spl mu/m SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies 0.6 mm/sup 2/ silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted at 1 ps accuracy.
    Original languageEnglish
    Title of host publication2005 NORCHIP
    PublisherIEEE Institute of Electrical and Electronic Engineers
    ISBN (Print)1-4244-0064-3, 978-1-4244-0064-5
    Publication statusPublished - 2005
    MoE publication typeA4 Article in a conference publication
    Event23rd Norchip Conference, IEEE NORCHIP 2005 - Oulu, Finland
    Duration: 21 Nov 200522 Nov 2005


    Conference23rd Norchip Conference, IEEE NORCHIP 2005


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