A DLL clock generator for a high speed A/D converter with 1 ps jitter and skew calibrator with 1 ps accuracy in 0.35 μm CMOS

Arto Rantala; David Gomes Martins; Markku Åberg

doi:10.1109/NORCHP.2005.1597002

A DLL clock generator for a high speed A/D converter with 1 ps jitter and skew calibrator with 1 ps accuracy in 0.35 μm CMOS

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

4 Citations (Scopus)

Abstract

This paper presents a clock generator circuit for a high speed analog-to-digital converter (ADC). A time interleaved ADC requires an accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at speed of 166 MS/s which corresponds to equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 /spl mu/m SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies 0.6 mm/sup 2/ silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted at 1 ps accuracy.

Original language	English
Title of host publication	2005 NORCHIP
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	114-117
ISBN (Print)	978-1-4244-0064-5
DOIs	https://doi.org/10.1109/NORCHP.2005.1597002
Publication status	Published - 2005
MoE publication type	A4 Article in a conference publication
Event	23rd Norchip Conference, IEEE NORCHIP 2005 - Oulu, Finland Duration: 21 Nov 2005 → 22 Nov 2005

Conference

Conference	23rd Norchip Conference, IEEE NORCHIP 2005
Country/Territory	Finland
City	Oulu
Period	21/11/05 → 22/11/05

Access to Document

10.1109/NORCHP.2005.1597002

Cite this

@inproceedings{8b58b6524c504ae3891cb2fdaf9f4b23,

title = "A DLL clock generator for a high speed A/D converter with 1 ps jitter and skew calibrator with 1 ps accuracy in 0.35 μm CMOS",

abstract = "This paper presents a clock generator circuit for a high speed analog-to-digital converter (ADC). A time interleaved ADC requires an accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at speed of 166 MS/s which corresponds to equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 /spl mu/m SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies 0.6 mm/sup 2/ silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted at 1 ps accuracy.",

author = "Arto Rantala and \{Gomes Martins\}, David and Markku {\AA}berg",

year = "2005",

doi = "10.1109/NORCHP.2005.1597002",

language = "English",

isbn = "978-1-4244-0064-5",

pages = "114--117",

booktitle = "2005 NORCHIP",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

note = "23rd Norchip Conference, IEEE NORCHIP 2005 ; Conference date: 21-11-2005 Through 22-11-2005",

}

Rantala, A , Gomes Martins, D & Åberg, M 2005, A DLL clock generator for a high speed A/D converter with 1 ps jitter and skew calibrator with 1 ps accuracy in 0.35 μm CMOS. in 2005 NORCHIP. IEEE Institute of Electrical and Electronic Engineers, pp. 114-117, 23rd Norchip Conference, IEEE NORCHIP 2005, Oulu, Finland, 21/11/05. https://doi.org/10.1109/NORCHP.2005.1597002

A DLL clock generator for a high speed A/D converter with 1 ps jitter and skew calibrator with 1 ps accuracy in 0.35 μm CMOS. / Rantala, Arto ; Gomes Martins, David; Åberg, Markku.
2005 NORCHIP. IEEE Institute of Electrical and Electronic Engineers, 2005. p. 114-117.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - A DLL clock generator for a high speed A/D converter with 1 ps jitter and skew calibrator with 1 ps accuracy in 0.35 μm CMOS

AU - Rantala, Arto

AU - Gomes Martins, David

AU - Åberg, Markku

PY - 2005

Y1 - 2005

N2 - This paper presents a clock generator circuit for a high speed analog-to-digital converter (ADC). A time interleaved ADC requires an accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at speed of 166 MS/s which corresponds to equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 /spl mu/m SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies 0.6 mm/sup 2/ silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted at 1 ps accuracy.

AB - This paper presents a clock generator circuit for a high speed analog-to-digital converter (ADC). A time interleaved ADC requires an accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at speed of 166 MS/s which corresponds to equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 /spl mu/m SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies 0.6 mm/sup 2/ silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted at 1 ps accuracy.

U2 - 10.1109/NORCHP.2005.1597002

DO - 10.1109/NORCHP.2005.1597002

M3 - Conference article in proceedings

SN - 978-1-4244-0064-5

SP - 114

EP - 117

BT - 2005 NORCHIP

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - 23rd Norchip Conference, IEEE NORCHIP 2005

Y2 - 21 November 2005 through 22 November 2005

ER -

A DLL clock generator for a high speed A/D converter with 1 ps jitter and skew calibrator with 1 ps accuracy in 0.35 μm CMOS

Abstract

Conference

Access to Document

Fingerprint

Cite this