@inproceedings{fa8e76a45a0f4d0fbb08aa6920e8ba29,
title = "A low-latency optical switch architecture using integrated μm SOI-based contention resolution and switching",
abstract = "The urgent need for high-bandwidth and high-port connectivity in Data Centers has boosted the deployment of optoelectronic packet switches towards bringing high data-rate optics closer to the ASIC, realizing optical transceiver functions directly at the ASIC package for high-rate, low-energy and low-latency interconnects. Even though optics can offer a broad range of low-energy integrated switch fabrics for replacing electronic switches and seamlessly interface with the optical I/Os, the use of energy-And latency-consuming electronic SerDes continues to be a necessity, mainly dictated by the absence of integrated and reliable optical buffering solutions. SerDes undertakes the role of optimally synergizing the lower-speed electronic buffers with the incoming and outgoing optical streams, suggesting that a SerDes-released chip-scale optical switch fabric can be only realized in case all necessary functions including contention resolution and switching can be implemented on a common photonic integration platform. In this paper, we demonstrate experimentally a hybrid Broadcast-And-Select (BS) / wavelength routed optical switch that performs both the optical buffering and switching functions with μm-scale Silicon-integrated building blocks. Optical buffering is carried out in a silicon-integrated variable delay line bank with a record-high on-chip delay/footprint efficiency of 2.6ns/mm2 and up to 17.2 nsec delay capability, while switching is executed via a BS design and a silicon-integrated echelle grating, assisted by SOA-MZI wavelength conversion stages and controlled by a FPGA header processing module. The switch has been experimentally validated in a 3x3 arrangement with 10Gb/s NRZ optical data packets, demonstrating error-free switching operation with a power penalty of <5dB.",
keywords = "All-optical Switching, Disaggregated Data Center, Echelle Grating, Feedforward Buffer, Integrated Delay Lines, On-chip Buffer, Optical Interconnects, Thick-SOI Platform, OtaNano",
author = "G. Mourgias-Alexandris and M. Moralis-Pegios and N. Terzenidis and M. Cherchi and M. Harjanne and Timo Aalto and K. Vyrsokinos and N. Pleros",
year = "2018",
month = jan,
day = "1",
doi = "10.1117/12.2289920",
language = "English",
isbn = "978-1-5106-1561-8",
series = "Proceedings of SPIE",
publisher = "International Society for Optics and Photonics SPIE",
pages = "7",
editor = "Henning Schr{\"o}der and Chen, {Ray T.}",
booktitle = "Optical Interconnects XVIII",
address = "United States",
note = "Optical Interconnects XVIII 2018 ; Conference date: 29-01-2018 Through 31-01-2018",
}