A low-latency optical switch architecture using integrated μm SOI-based contention resolution and switching

G. Mourgias-Alexandris, M. Moralis-Pegios, N. Terzenidis, M. Cherchi, M. Harjanne, Timo Aalto, K. Vyrsokinos, N. Pleros

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review


    The urgent need for high-bandwidth and high-port connectivity in Data Centers has boosted the deployment of optoelectronic packet switches towards bringing high data-rate optics closer to the ASIC, realizing optical transceiver functions directly at the ASIC package for high-rate, low-energy and low-latency interconnects. Even though optics can offer a broad range of low-energy integrated switch fabrics for replacing electronic switches and seamlessly interface with the optical I/Os, the use of energy-And latency-consuming electronic SerDes continues to be a necessity, mainly dictated by the absence of integrated and reliable optical buffering solutions. SerDes undertakes the role of optimally synergizing the lower-speed electronic buffers with the incoming and outgoing optical streams, suggesting that a SerDes-released chip-scale optical switch fabric can be only realized in case all necessary functions including contention resolution and switching can be implemented on a common photonic integration platform. In this paper, we demonstrate experimentally a hybrid Broadcast-And-Select (BS) / wavelength routed optical switch that performs both the optical buffering and switching functions with μm-scale Silicon-integrated building blocks. Optical buffering is carried out in a silicon-integrated variable delay line bank with a record-high on-chip delay/footprint efficiency of 2.6ns/mm2 and up to 17.2 nsec delay capability, while switching is executed via a BS design and a silicon-integrated echelle grating, assisted by SOA-MZI wavelength conversion stages and controlled by a FPGA header processing module. The switch has been experimentally validated in a 3x3 arrangement with 10Gb/s NRZ optical data packets, demonstrating error-free switching operation with a power penalty of <5dB.

    Original languageEnglish
    Title of host publicationOptical Interconnects XVIII
    EditorsHenning Schröder, Ray T. Chen
    PublisherInternational Society for Optics and Photonics SPIE
    ISBN (Print)978-1-5106-1561-8
    Publication statusPublished - 1 Jan 2018
    MoE publication typeA4 Article in a conference publication
    EventOptical Interconnects XVIII 2018 - San Francisco, United States
    Duration: 29 Jan 201831 Jan 2018

    Publication series

    SeriesProceedings of SPIE


    ConferenceOptical Interconnects XVIII 2018
    Country/TerritoryUnited States
    CitySan Francisco


    This work was supported by the European Commission through projects H2020 projects 688172) and L3MATRIX (Contract 688544).


    • All-optical Switching
    • Disaggregated Data Center
    • Echelle Grating
    • Feedforward Buffer
    • Integrated Delay Lines
    • On-chip Buffer
    • Optical Interconnects
    • Thick-SOI Platform
    • OtaNano


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