A low-latency optical switch architecture using integrated μm SOI-based contention resolution and switching

G. Mourgias-Alexandris, M. Moralis-Pegios, N. Terzenidis, M. Cherchi, M. Harjanne, Timo Aalto, K. Vyrsokinos, N. Pleros

Research output: Chapter in Book/Report/Conference proceedingChapter or book articleResearchpeer-review

Abstract

The urgent need for high-bandwidth and high-port connectivity in Data Centers has boosted the deployment of optoelectronic packet switches towards bringing high data-rate optics closer to the ASIC, realizing optical transceiver functions directly at the ASIC package for high-rate, low-energy and low-latency interconnects. Even though optics can offer a broad range of low-energy integrated switch fabrics for replacing electronic switches and seamlessly interface with the optical I/Os, the use of energy-And latency-consuming electronic SerDes continues to be a necessity, mainly dictated by the absence of integrated and reliable optical buffering solutions. SerDes undertakes the role of optimally synergizing the lower-speed electronic buffers with the incoming and outgoing optical streams, suggesting that a SerDes-released chip-scale optical switch fabric can be only realized in case all necessary functions including contention resolution and switching can be implemented on a common photonic integration platform. In this paper, we demonstrate experimentally a hybrid Broadcast-And-Select (BS) / wavelength routed optical switch that performs both the optical buffering and switching functions with μm-scale Silicon-integrated building blocks. Optical buffering is carried out in a silicon-integrated variable delay line bank with a record-high on-chip delay/footprint efficiency of 2.6ns/mm2 and up to 17.2 nsec delay capability, while switching is executed via a BS design and a silicon-integrated echelle grating, assisted by SOA-MZI wavelength conversion stages and controlled by a FPGA header processing module. The switch has been experimentally validated in a 3x3 arrangement with 10Gb/s NRZ optical data packets, demonstrating error-free switching operation with a power penalty of <5dB.

LanguageEnglish
Title of host publicationOptical Interconnects XVIII
EditorsHenning Schröder, Ray T. Chen
PublisherInternational Society for Optics and Photonics SPIE
Pages7
ISBN (Print)978-1-5106-1561-8
DOIs
Publication statusPublished - 1 Jan 2018
EventOptical Interconnects XVIII 2018 - San Francisco, United States
Duration: 29 Jan 201831 Jan 2018

Publication series

NameProceedings of SPIE - The International Society for Optical Engineering
PublisherInternational Society for Optics and Photonics SPIE
ISSN (Print)0277-786X

Conference

ConferenceOptical Interconnects XVIII 2018
CountryUnited States
CitySan Francisco
Period29/01/1831/01/18

Fingerprint

Optical Switch
Optical switches
SOI (semiconductors)
Contention
Latency
Silicon
switches
Switches
Application specific integrated circuits
Switch
application specific integrated circuits
Optics
Optical transceivers
silicon
Switching functions
Electronics
Optical frequency conversion
chips
echelle gratings
optics

Keywords

  • All-optical Switching
  • Disaggregated Data Center
  • Echelle Grating
  • Feedforward Buffer
  • Integrated Delay Lines
  • On-chip Buffer
  • Optical Interconnects
  • Thick-SOI Platform

Cite this

Mourgias-Alexandris, G., Moralis-Pegios, M., Terzenidis, N., Cherchi, M., Harjanne, M., Aalto, T., ... Pleros, N. (2018). A low-latency optical switch architecture using integrated μm SOI-based contention resolution and switching. In H. Schröder, & R. T. Chen (Eds.), Optical Interconnects XVIII (pp. 7). (Proceedings of SPIE - The International Society for Optical Engineering). International Society for Optics and Photonics SPIE. https://doi.org/10.1117/12.2289920
Mourgias-Alexandris, G. ; Moralis-Pegios, M. ; Terzenidis, N. ; Cherchi, M. ; Harjanne, M. ; Aalto, Timo ; Vyrsokinos, K. ; Pleros, N. / A low-latency optical switch architecture using integrated μm SOI-based contention resolution and switching. Optical Interconnects XVIII. editor / Henning Schröder ; Ray T. Chen. International Society for Optics and Photonics SPIE, 2018. pp. 7 (Proceedings of SPIE - The International Society for Optical Engineering).
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Mourgias-Alexandris, G, Moralis-Pegios, M, Terzenidis, N, Cherchi, M, Harjanne, M, Aalto, T, Vyrsokinos, K & Pleros, N 2018, A low-latency optical switch architecture using integrated μm SOI-based contention resolution and switching. in H Schröder & RT Chen (eds), Optical Interconnects XVIII. Proceedings of SPIE - The International Society for Optical Engineering, International Society for Optics and Photonics SPIE, pp. 7, Optical Interconnects XVIII 2018, San Francisco, United States, 29/01/18. https://doi.org/10.1117/12.2289920

A low-latency optical switch architecture using integrated μm SOI-based contention resolution and switching. / Mourgias-Alexandris, G.; Moralis-Pegios, M.; Terzenidis, N.; Cherchi, M.; Harjanne, M.; Aalto, Timo; Vyrsokinos, K.; Pleros, N.

Optical Interconnects XVIII. ed. / Henning Schröder; Ray T. Chen. International Society for Optics and Photonics SPIE, 2018. p. 7 (Proceedings of SPIE - The International Society for Optical Engineering).

Research output: Chapter in Book/Report/Conference proceedingChapter or book articleResearchpeer-review

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AU - Cherchi, M.

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Mourgias-Alexandris G, Moralis-Pegios M, Terzenidis N, Cherchi M, Harjanne M, Aalto T et al. A low-latency optical switch architecture using integrated μm SOI-based contention resolution and switching. In Schröder H, Chen RT, editors, Optical Interconnects XVIII. International Society for Optics and Photonics SPIE. 2018. p. 7. (Proceedings of SPIE - The International Society for Optical Engineering). https://doi.org/10.1117/12.2289920