Abstract
The urgent need for high-bandwidth and high-port connectivity in Data Centers has boosted the deployment of optoelectronic packet switches towards bringing high data-rate optics closer to the ASIC, realizing optical transceiver functions directly at the ASIC package for high-rate, low-energy and low-latency interconnects. Even though optics can offer a broad range of low-energy integrated switch fabrics for replacing electronic switches and seamlessly interface with the optical I/Os, the use of energy-And latency-consuming electronic SerDes continues to be a necessity, mainly dictated by the absence of integrated and reliable optical buffering solutions. SerDes undertakes the role of optimally synergizing the lower-speed electronic buffers with the incoming and outgoing optical streams, suggesting that a SerDes-released chip-scale optical switch fabric can be only realized in case all necessary functions including contention resolution and switching can be implemented on a common photonic integration platform. In this paper, we demonstrate experimentally a hybrid Broadcast-And-Select (BS) / wavelength routed optical switch that performs both the optical buffering and switching functions with μm-scale Silicon-integrated building blocks. Optical buffering is carried out in a silicon-integrated variable delay line bank with a record-high on-chip delay/footprint efficiency of 2.6ns/mm2 and up to 17.2 nsec delay capability, while switching is executed via a BS design and a silicon-integrated echelle grating, assisted by SOA-MZI wavelength conversion stages and controlled by a FPGA header processing module. The switch has been experimentally validated in a 3x3 arrangement with 10Gb/s NRZ optical data packets, demonstrating error-free switching operation with a power penalty of <5dB.
| Original language | English |
|---|---|
| Title of host publication | Optical Interconnects XVIII |
| Editors | Henning Schröder, Ray T. Chen |
| Publisher | International Society for Optics and Photonics SPIE |
| Pages | 7 |
| ISBN (Print) | 978-1-5106-1561-8 |
| DOIs | |
| Publication status | Published - 1 Jan 2018 |
| MoE publication type | Not Eligible |
| Event | Optical Interconnects XVIII 2018 - San Francisco, United States Duration: 29 Jan 2018 → 31 Jan 2018 |
Publication series
| Series | Proceedings of SPIE |
|---|---|
| Volume | 10538 |
| ISSN | 0277-786X |
Conference
| Conference | Optical Interconnects XVIII 2018 |
|---|---|
| Country | United States |
| City | San Francisco |
| Period | 29/01/18 → 31/01/18 |
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Keywords
- All-optical Switching
- Disaggregated Data Center
- Echelle Grating
- Feedforward Buffer
- Integrated Delay Lines
- On-chip Buffer
- Optical Interconnects
- Thick-SOI Platform
Cite this
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A low-latency optical switch architecture using integrated μm SOI-based contention resolution and switching. / Mourgias-Alexandris, G.; Moralis-Pegios, M.; Terzenidis, N.; Cherchi, M.; Harjanne, M.; Aalto, Timo; Vyrsokinos, K.; Pleros, N.
Optical Interconnects XVIII. ed. / Henning Schröder; Ray T. Chen. International Society for Optics and Photonics SPIE, 2018. p. 7 (Proceedings of SPIE, Vol. 10538).Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review
TY - GEN
T1 - A low-latency optical switch architecture using integrated μm SOI-based contention resolution and switching
AU - Mourgias-Alexandris, G.
AU - Moralis-Pegios, M.
AU - Terzenidis, N.
AU - Cherchi, M.
AU - Harjanne, M.
AU - Aalto, Timo
AU - Vyrsokinos, K.
AU - Pleros, N.
PY - 2018/1/1
Y1 - 2018/1/1
N2 - The urgent need for high-bandwidth and high-port connectivity in Data Centers has boosted the deployment of optoelectronic packet switches towards bringing high data-rate optics closer to the ASIC, realizing optical transceiver functions directly at the ASIC package for high-rate, low-energy and low-latency interconnects. Even though optics can offer a broad range of low-energy integrated switch fabrics for replacing electronic switches and seamlessly interface with the optical I/Os, the use of energy-And latency-consuming electronic SerDes continues to be a necessity, mainly dictated by the absence of integrated and reliable optical buffering solutions. SerDes undertakes the role of optimally synergizing the lower-speed electronic buffers with the incoming and outgoing optical streams, suggesting that a SerDes-released chip-scale optical switch fabric can be only realized in case all necessary functions including contention resolution and switching can be implemented on a common photonic integration platform. In this paper, we demonstrate experimentally a hybrid Broadcast-And-Select (BS) / wavelength routed optical switch that performs both the optical buffering and switching functions with μm-scale Silicon-integrated building blocks. Optical buffering is carried out in a silicon-integrated variable delay line bank with a record-high on-chip delay/footprint efficiency of 2.6ns/mm2 and up to 17.2 nsec delay capability, while switching is executed via a BS design and a silicon-integrated echelle grating, assisted by SOA-MZI wavelength conversion stages and controlled by a FPGA header processing module. The switch has been experimentally validated in a 3x3 arrangement with 10Gb/s NRZ optical data packets, demonstrating error-free switching operation with a power penalty of <5dB.
AB - The urgent need for high-bandwidth and high-port connectivity in Data Centers has boosted the deployment of optoelectronic packet switches towards bringing high data-rate optics closer to the ASIC, realizing optical transceiver functions directly at the ASIC package for high-rate, low-energy and low-latency interconnects. Even though optics can offer a broad range of low-energy integrated switch fabrics for replacing electronic switches and seamlessly interface with the optical I/Os, the use of energy-And latency-consuming electronic SerDes continues to be a necessity, mainly dictated by the absence of integrated and reliable optical buffering solutions. SerDes undertakes the role of optimally synergizing the lower-speed electronic buffers with the incoming and outgoing optical streams, suggesting that a SerDes-released chip-scale optical switch fabric can be only realized in case all necessary functions including contention resolution and switching can be implemented on a common photonic integration platform. In this paper, we demonstrate experimentally a hybrid Broadcast-And-Select (BS) / wavelength routed optical switch that performs both the optical buffering and switching functions with μm-scale Silicon-integrated building blocks. Optical buffering is carried out in a silicon-integrated variable delay line bank with a record-high on-chip delay/footprint efficiency of 2.6ns/mm2 and up to 17.2 nsec delay capability, while switching is executed via a BS design and a silicon-integrated echelle grating, assisted by SOA-MZI wavelength conversion stages and controlled by a FPGA header processing module. The switch has been experimentally validated in a 3x3 arrangement with 10Gb/s NRZ optical data packets, demonstrating error-free switching operation with a power penalty of <5dB.
KW - All-optical Switching
KW - Disaggregated Data Center
KW - Echelle Grating
KW - Feedforward Buffer
KW - Integrated Delay Lines
KW - On-chip Buffer
KW - Optical Interconnects
KW - Thick-SOI Platform
UR - http://www.scopus.com/inward/record.url?scp=85047397411&partnerID=8YFLogxK
U2 - 10.1117/12.2289920
DO - 10.1117/12.2289920
M3 - Conference article in proceedings
AN - SCOPUS:85047397411
SN - 978-1-5106-1561-8
T3 - Proceedings of SPIE
SP - 7
BT - Optical Interconnects XVIII
A2 - Schröder, Henning
A2 - Chen, Ray T.
PB - International Society for Optics and Photonics SPIE
ER -