A network on chip architecture and design methodology

Shashi Kumar, Axel Jantsch, Juha-Pekka Soininen, Martti Forsell, Mikael Millberg, Johnny Öberg, Kari Tiensyrjä, Ahmded Hemani

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

855 Citations (Scopus)

Abstract

We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m/spl times/n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of switches and resources providing physical- and architectural-level design integration. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, an FPGA, a custom hardware block or any other intellectual property (IP) block, which fits into the available slot and complies with the interface of the NOC. The NOC architecture essentially is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack. We define the concept of a region, which occupies an area of any number of resources and switches. This concept allows the NOC to accommodate large resources such as large memory banks, FPGA areas, or special purpose computation resources such as high performance multi-processors. The NOC design methodology consists of two phases. In the first phase a concrete architecture is derived from the general NOC template. The concrete architecture defines the number of switches and shape of the network, the kind and shape of regions and the number and kind of resources. The second phase maps the application onto the concrete architecture to form a concrete product.
Original languageEnglish
Title of host publicationProceedings IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publicationNew Paradigms for VLSI Systems Design
PublisherIEEE Institute of Electrical and Electronic Engineers
Pages117-124
ISBN (Print)0-7695-1486-3
DOIs
Publication statusPublished - 2002
MoE publication typeA4 Article in a conference publication
Event2002 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2002 - Pittsburgh, United States
Duration: 25 Apr 200226 Apr 2002

Conference

Conference2002 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2002
CountryUnited States
CityPittsburgh
Period25/04/0226/04/02

Keywords

  • network on chip
  • architecture design
  • platform based design

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    Kumar, S., Jantsch, A., Soininen, J-P., Forsell, M., Millberg, M., Öberg, J., Tiensyrjä, K., & Hemani, A. (2002). A network on chip architecture and design methodology. In Proceedings IEEE Computer Society Annual Symposium on VLSI : New Paradigms for VLSI Systems Design (pp. 117-124). IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.1109/ISVLSI.2002.1016885