A network on chip (NOC) scheme relying on reuse of existing intellectual property blocks and a unified communication solution has been proposed for solving architectural and design productivity problems of future systems on chips. A NOC consists of a set of heterogeneous computing and storage resources that are connected to each other via a standardized communication network. A heterogeneous structure is suitable for application specific computing, but not for high-speed general purpose computing that is increasingly used in devices that will be powered by NOCs. General purpose functionality can, however, be provided by dedicating the whole chip or a special area on a heterogeneous NOC, called region, for a homogeneous general purpose computing engine. Unfortunately the architectures proposed for NOCs and on-chip parallel computers feature poor performance and portability, or are difficult to program in general purpose computing due to limited communication bandwidth, inability to eliminate delays caused by the latency of the network, high communication overheads, and poor models of parallel computing. In this chapter we will discuss the problems and solutions of implementing an efficient single chip general purpose parallel computing engine. We will also describe our ECLIPSE architecture that can be used either as a truly scalable, high-speed, single chip parallel computer or as a NOC region responsible of general-purpose computation.
|Title of host publication||Networks on Chip|
|Editors||Axel Jantsch, Antti Tenhunen|
|Publication status||Published - 2003|
|MoE publication type||Not Eligible|