A Parallel Configuration Model for Reducing the Run-Time Reconfiguration Overhead

Yang Qu, Juha-Pekka Soininen, Jari Nurmi

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    17 Citations (Scopus)

    Abstract

    Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configuration latency is a major limitation and it can largely degrade the system performance. One reason is that tasks can run in parallel but configurations of the tasks can be done only in sequence. This work presents a novel configuration model to enable configuration parallelism. It consists of multiple homogeneous tiles and each tile has its own configuration SRAM that can be individually accessed. Thus multiple configuration controllers can load tasks in parallel and more speedups can be achieved. We used a prefetch scheduling technique to evaluate the model with randomly generated tasks. The experiment results reveal that in average using multiple controllers can reduce the configuration overheads by 21%. Compared to best cases of using multiple tiles with a single controller, additional 40% speedup can be achieved using multiple controllers.
    Original languageEnglish
    Title of host publicationProceedings of the Design Automation & Test in Europe Conference 2006
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Pages965-970
    ISBN (Print)3-9810801-1-4
    DOIs
    Publication statusPublished - 2006
    MoE publication typeA4 Article in a conference publication

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