Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configuration latency is a major limitation and it can largely degrade the system performance. One reason is that tasks can run in parallel but configurations of the tasks can be done only in sequence. This work presents a novel configuration model to enable configuration parallelism. It consists of multiple homogeneous tiles and each tile has its own configuration SRAM that can be individually accessed. Thus multiple configuration controllers can load tasks in parallel and more speedups can be achieved. We used a prefetch scheduling technique to evaluate the model with randomly generated tasks. The experiment results reveal that in average using multiple controllers can reduce the configuration overheads by 21%. Compared to best cases of using multiple tiles with a single controller, additional 40% speedup can be achieved using multiple controllers.
|Title of host publication||Proceedings of the Design Automation & Test in Europe Conference 2006|
|Publisher||IEEE Institute of Electrical and Electronic Engineers|
|Publication status||Published - 2006|
|MoE publication type||A4 Article in a conference publication|
Qu, Y., Soininen, J-P., & Nurmi, J. (2006). A Parallel Configuration Model for Reducing the Run-Time Reconfiguration Overhead. In Proceedings of the Design Automation & Test in Europe Conference 2006 (pp. 965-970). IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.1109/DATE.2006.243864