A robust ultra-low voltage CPU utilizing timing-error prevention

Markus Hiiekari, Jukka Teittinen, Lauri Koskinen, Matthew J. Turnquist, Jani Mäkipää, Arto Rantala, Matti Sopanen, Mikko Kaltiokallio

    Research output: Contribution to journalArticleScientificpeer-review

    Abstract

    To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. © 2015 by the authors; licensee MDPI, Basel, Switzerland.
    Original languageEnglish
    Pages (from-to)57-68
    JournalJournal of Low Power Electronics and Applications
    Volume5
    Issue number2
    DOIs
    Publication statusPublished - 2015
    MoE publication typeA1 Journal article-refereed

    Fingerprint

    Threshold voltage
    Program processors
    Reduced instruction set computing
    Digital circuits
    Electric potential
    Stretching
    Energy efficiency
    Clocks
    Energy conservation
    Energy utilization

    Keywords

    • clock stretching
    • digital CMOS
    • energy-efficiency
    • near-threshold
    • timing-error prevention (TEP)
    • ultra-low power (ULP)
    • variability

    Cite this

    Hiiekari, M., Teittinen, J., Koskinen, L., Turnquist, M. J., Mäkipää, J., Rantala, A., ... Kaltiokallio, M. (2015). A robust ultra-low voltage CPU utilizing timing-error prevention. Journal of Low Power Electronics and Applications, 5(2), 57-68. https://doi.org/10.3390/jlpea5020057
    Hiiekari, Markus ; Teittinen, Jukka ; Koskinen, Lauri ; Turnquist, Matthew J. ; Mäkipää, Jani ; Rantala, Arto ; Sopanen, Matti ; Kaltiokallio, Mikko. / A robust ultra-low voltage CPU utilizing timing-error prevention. In: Journal of Low Power Electronics and Applications. 2015 ; Vol. 5, No. 2. pp. 57-68.
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    abstract = "To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39{\%} energy saving compared to operation based on static signoff timing. {\circledC} 2015 by the authors; licensee MDPI, Basel, Switzerland.",
    keywords = "clock stretching, digital CMOS, energy-efficiency, near-threshold, timing-error prevention (TEP), ultra-low power (ULP), variability",
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    Hiiekari, M, Teittinen, J, Koskinen, L, Turnquist, MJ, Mäkipää, J, Rantala, A, Sopanen, M & Kaltiokallio, M 2015, 'A robust ultra-low voltage CPU utilizing timing-error prevention', Journal of Low Power Electronics and Applications, vol. 5, no. 2, pp. 57-68. https://doi.org/10.3390/jlpea5020057

    A robust ultra-low voltage CPU utilizing timing-error prevention. / Hiiekari, Markus; Teittinen, Jukka; Koskinen, Lauri; Turnquist, Matthew J.; Mäkipää, Jani; Rantala, Arto; Sopanen, Matti; Kaltiokallio, Mikko.

    In: Journal of Low Power Electronics and Applications, Vol. 5, No. 2, 2015, p. 57-68.

    Research output: Contribution to journalArticleScientificpeer-review

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    AU - Hiiekari, Markus

    AU - Teittinen, Jukka

    AU - Koskinen, Lauri

    AU - Turnquist, Matthew J.

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    AU - Rantala, Arto

    AU - Sopanen, Matti

    AU - Kaltiokallio, Mikko

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    AB - To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. © 2015 by the authors; licensee MDPI, Basel, Switzerland.

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