A robust ultra-low voltage CPU utilizing timing-error prevention

Markus Hiiekari, Jukka Teittinen, Lauri Koskinen, Matthew J. Turnquist, Jani Mäkipää, Arto Rantala, Matti Sopanen, Mikko Kaltiokallio

    Research output: Contribution to journalArticleScientificpeer-review


    To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. © 2015 by the authors; licensee MDPI, Basel, Switzerland.
    Original languageEnglish
    Pages (from-to)57-68
    JournalJournal of Low Power Electronics and Applications
    Issue number2
    Publication statusPublished - 2015
    MoE publication typeA1 Journal article-refereed


    • clock stretching
    • digital CMOS
    • energy-efficiency
    • near-threshold
    • timing-error prevention (TEP)
    • ultra-low power (ULP)
    • variability


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