A robust ultra-low voltage CPU utilizing timing-error prevention

Markus Hiiekari; Jukka Teittinen; Lauri Koskinen; Matthew J. Turnquist; Jani Mäkipää; Arto Rantala; Matti Sopanen; Mikko Kaltiokallio

doi:10.3390/jlpea5020057

A robust ultra-low voltage CPU utilizing timing-error prevention

Markus Hiiekari, Jukka Teittinen, Lauri Koskinen, Matthew J. Turnquist, Jani Mäkipää, Arto Rantala, Matti Sopanen, Mikko Kaltiokallio

Research output: Contribution to journal › Article › Scientific › peer-review

Abstract

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. © 2015 by the authors; licensee MDPI, Basel, Switzerland.

Original language	English
Pages (from-to)	57-68
Journal	Journal of Low Power Electronics and Applications
Volume	5
Issue number	2
DOIs	https://doi.org/10.3390/jlpea5020057
Publication status	Published - 2015
MoE publication type	A1 Journal article-refereed

Keywords

clock stretching
digital CMOS
energy-efficiency
near-threshold
timing-error prevention (TEP)
ultra-low power (ULP)
variability

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.3390/jlpea5020057

Cite this

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title = "A robust ultra-low voltage CPU utilizing timing-error prevention",

abstract = "To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. {\textcopyright} 2015 by the authors; licensee MDPI, Basel, Switzerland.",

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language = "English",

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T1 - A robust ultra-low voltage CPU utilizing timing-error prevention

AU - Hiiekari, Markus

AU - Teittinen, Jukka

AU - Koskinen, Lauri

AU - Turnquist, Matthew J.

AU - Mäkipää, Jani

AU - Rantala, Arto

AU - Sopanen, Matti

AU - Kaltiokallio, Mikko

PY - 2015

Y1 - 2015

N2 - To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. © 2015 by the authors; licensee MDPI, Basel, Switzerland.

AB - To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. © 2015 by the authors; licensee MDPI, Basel, Switzerland.

KW - clock stretching

KW - digital CMOS

KW - energy-efficiency

KW - near-threshold

KW - timing-error prevention (TEP)

KW - ultra-low power (ULP)

KW - variability

U2 - 10.3390/jlpea5020057

DO - 10.3390/jlpea5020057

M3 - Article

SN - 2079-9268

VL - 5

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EP - 68

JO - Journal of Low Power Electronics and Applications

JF - Journal of Low Power Electronics and Applications

IS - 2

ER -

A robust ultra-low voltage CPU utilizing timing-error prevention

Abstract

Keywords

UN SDGs

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