A scalable high-performance computing solution for networks on chips

Martti Forsell

doi:10.1109/MM.2002.1044299

A scalable high-performance computing solution for networks on chips

Martti Forsell

Research output: Contribution to journal › Article › Scientific › peer-review

96 Citations (Scopus)

Abstract

The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs

Original language	English
Pages (from-to)	46-55
Journal	IEEE Micro
Volume	22
Issue number	5
DOIs	https://doi.org/10.1109/MM.2002.1044299
Publication status	Published - 2002
MoE publication type	A1 Journal article-refereed

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10.1109/MM.2002.1044299

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@article{afbbcaeca3d24137bad1c8b4430f1908,

title = "A scalable high-performance computing solution for networks on chips",

abstract = "The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs",

author = "Martti Forsell",

year = "2002",

doi = "10.1109/MM.2002.1044299",

language = "English",

volume = "22",

pages = "46--55",

journal = "IEEE Micro",

issn = "0272-1732",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

number = "5",

}

TY - JOUR

T1 - A scalable high-performance computing solution for networks on chips

AU - Forsell, Martti

PY - 2002

Y1 - 2002

N2 - The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs

AB - The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs

U2 - 10.1109/MM.2002.1044299

DO - 10.1109/MM.2002.1044299

M3 - Article

SN - 0272-1732

VL - 22

SP - 46

EP - 55

JO - IEEE Micro

JF - IEEE Micro

IS - 5

ER -

A scalable high-performance computing solution for networks on chips

Abstract

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