A scalable high-performance computing solution for networks on chips

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    90 Citations (Scopus)

    Abstract

    The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs
    Original languageEnglish
    Pages (from-to)46-55
    JournalIEEE Micro
    Volume22
    Issue number5
    DOIs
    Publication statusPublished - 2002
    MoE publication typeA1 Journal article-refereed

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