A scalable high-performance computing solution for networks on chips

Research output: Contribution to journalArticleScientificpeer-review

90 Citations (Scopus)

Abstract

The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs
Original languageEnglish
Pages (from-to)46-55
JournalIEEE Micro
Volume22
Issue number5
DOIs
Publication statusPublished - 2002
MoE publication typeA1 Journal article-refereed

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Parallel programming
Program processors
Data storage equipment
Network-on-chip

Cite this

@article{afbbcaeca3d24137bad1c8b4430f1908,
title = "A scalable high-performance computing solution for networks on chips",
abstract = "The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs",
author = "Martti Forsell",
year = "2002",
doi = "10.1109/MM.2002.1044299",
language = "English",
volume = "22",
pages = "46--55",
journal = "IEEE Micro",
issn = "0272-1732",
publisher = "Institute of Electrical and Electronic Engineers IEEE",
number = "5",

}

A scalable high-performance computing solution for networks on chips. / Forsell, Martti.

In: IEEE Micro, Vol. 22, No. 5, 2002, p. 46-55.

Research output: Contribution to journalArticleScientificpeer-review

TY - JOUR

T1 - A scalable high-performance computing solution for networks on chips

AU - Forsell, Martti

PY - 2002

Y1 - 2002

N2 - The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs

AB - The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs

U2 - 10.1109/MM.2002.1044299

DO - 10.1109/MM.2002.1044299

M3 - Article

VL - 22

SP - 46

EP - 55

JO - IEEE Micro

JF - IEEE Micro

SN - 0272-1732

IS - 5

ER -