A scalable high-performance computing solution for networks on chips

Martti Forsell

doi:10.1109/MM.2002.1044299

A scalable high-performance computing solution for networks on chips

Martti Forsell

Research output: Contribution to journal › Article › Scientific › peer-review

97 Citations (Scopus)

Abstract

The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs

Original language	English
Pages (from-to)	46-55
Journal	IEEE Micro
Volume	22
Issue number	5
DOIs	https://doi.org/10.1109/MM.2002.1044299
Publication status	Published - 2002
MoE publication type	A1 Journal article-refereed

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10.1109/MM.2002.1044299

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title = "A scalable high-performance computing solution for networks on chips",

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A scalable high-performance computing solution for networks on chips

Abstract

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