### Abstract

A silicon efficient real-time approach to decode convolutional codes is presented. The algorithm is a special recurrent neural network, which needs no supervision. A standard solution for the convolutional decoding has been the Viterbi algorithm, which is an optimal solution. The complexity of a Viterbi decoder increases exponentially as a function of the constraint length. The complexity of the utilized algorithm increased more likely polynomically, which makes it attractive for applications with a long constraint length. The algorithm requires massive parallel and fast computing, which is hard to achieve effectively using a standard digital logic. Novel floating-gate structures are used to perform highly parallel signal processing within minimal silicon area. Silicon area of a decoder having constraint length of 3 and rate 1/2 is only 950 × 450 µ m

^{2}using 0.35 µm CMOS. Measurements show that a BER of 0.06 can be obtained at decoding speed of 1.25 MHz with a input signal having SNR of 0dB.Original language | English |
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Title of host publication | Proceedings of the 27th European Solid-State Circuits Conference |

Publisher | IEEE Institute of Electrical and Electronic Engineers |

Pages | 452-455 |

ISBN (Print) | 2-914601-00-X |

Publication status | Published - 2001 |

MoE publication type | A4 Article in a conference publication |

Event | 27th European Solid-State Circuits Conference, ESSCIRC 2001 - Villach, Austria Duration: 18 Sep 2001 → 20 Sep 2001 |

### Conference

Conference | 27th European Solid-State Circuits Conference, ESSCIRC 2001 |
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Country | Austria |

City | Villach |

Period | 18/09/01 → 20/09/01 |

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## Cite this

Rantala, A., Vatunen, S., Harinen, T., & Åberg, M. (2001). A silicon efficient high speed L=3 rate 1/2 convolutional decoder using recurrent neural networks. In

*Proceedings of the 27th European Solid-State Circuits Conference*(pp. 452-455). IEEE Institute of Electrical and Electronic Engineers. https://ieeexplore.ieee.org/document/1471427