A silicon efficient high speed L=3 rate 1/2 convolutional decoder using recurrent neural networks

Arto Rantala; Silja Vatunen; Timo Harinen; Markku Åberg

A silicon efficient high speed L=3 rate 1/2 convolutional decoder using recurrent neural networks

Arto Rantala^*, Silja Vatunen, Timo Harinen, Markku Åberg

^*Corresponding author for this work

VTT (former employee or external)

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

6 Citations (Scopus)

Abstract

A silicon efficient real-time approach to decode convolutional codes is presented. The algorithm is a special recurrent neural network, which needs no supervision. A standard solution for the convolutional decoding has been the Viterbi algorithm, which is an optimal solution. The complexity of a Viterbi decoder increases exponentially as a function of the constraint length. The complexity of the utilized algorithm increased more likely polynomically, which makes it attractive for applications with a long constraint length. The algorithm requires massive parallel and fast computing, which is hard to achieve effectively using a standard digital logic. Novel floating-gate structures are used to perform highly parallel signal processing within minimal silicon area. Silicon area of a decoder having constraint length of 3 and rate 1/2 is only 950 × 450 µ m² using 0.35 µm CMOS. Measurements show that a BER of 0.06 can be obtained at decoding speed of 1.25 MHz with a input signal having SNR of 0dB.

Original language	English
Title of host publication	Proceedings of the 27th European Solid-State Circuits Conference
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	452-455
ISBN (Print)	2-914601-00-X
Publication status	Published - 2001
MoE publication type	A4 Article in a conference publication
Event	27th European Solid-State Circuits Conference, ESSCIRC 2001 - Villach, Austria Duration: 18 Sept 2001 → 20 Sept 2001

Conference

Conference	27th European Solid-State Circuits Conference, ESSCIRC 2001
Country/Territory	Austria
City	Villach
Period	18/09/01 → 20/09/01

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Cite this

@inproceedings{1f75dfc077f84b69882af320feaa4305,

title = "A silicon efficient high speed L=3 rate 1/2 convolutional decoder using recurrent neural networks",

abstract = "A silicon efficient real-time approach to decode convolutional codes is presented. The algorithm is a special recurrent neural network, which needs no supervision. A standard solution for the convolutional decoding has been the Viterbi algorithm, which is an optimal solution. The complexity of a Viterbi decoder increases exponentially as a function of the constraint length. The complexity of the utilized algorithm increased more likely polynomically, which makes it attractive for applications with a long constraint length. The algorithm requires massive parallel and fast computing, which is hard to achieve effectively using a standard digital logic. Novel floating-gate structures are used to perform highly parallel signal processing within minimal silicon area. Silicon area of a decoder having constraint length of 3 and rate 1/2 is only 950 × 450 µ m2 using 0.35 µm CMOS. Measurements show that a BER of 0.06 can be obtained at decoding speed of 1.25 MHz with a input signal having SNR of 0dB.",

author = "Arto Rantala and Silja Vatunen and Timo Harinen and Markku {\AA}berg",

year = "2001",

language = "English",

isbn = "2-914601-00-X",

pages = "452--455",

booktitle = "Proceedings of the 27th European Solid-State Circuits Conference",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

note = "27th European Solid-State Circuits Conference, ESSCIRC 2001 ; Conference date: 18-09-2001 Through 20-09-2001",

}

Rantala, A, Vatunen, S, Harinen, T & Åberg, M 2001, A silicon efficient high speed L=3 rate 1/2 convolutional decoder using recurrent neural networks. in Proceedings of the 27th European Solid-State Circuits Conference. IEEE Institute of Electrical and Electronic Engineers, pp. 452-455, 27th European Solid-State Circuits Conference, ESSCIRC 2001, Villach, Austria, 18/09/01. <https://ieeexplore.ieee.org/document/1471427>

A silicon efficient high speed L=3 rate 1/2 convolutional decoder using recurrent neural networks. / Rantala, Arto; Vatunen, Silja; Harinen, Timo et al.
Proceedings of the 27th European Solid-State Circuits Conference. IEEE Institute of Electrical and Electronic Engineers, 2001. p. 452-455.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - A silicon efficient high speed L=3 rate 1/2 convolutional decoder using recurrent neural networks

AU - Rantala, Arto

AU - Vatunen, Silja

AU - Harinen, Timo

AU - Åberg, Markku

PY - 2001

Y1 - 2001

N2 - A silicon efficient real-time approach to decode convolutional codes is presented. The algorithm is a special recurrent neural network, which needs no supervision. A standard solution for the convolutional decoding has been the Viterbi algorithm, which is an optimal solution. The complexity of a Viterbi decoder increases exponentially as a function of the constraint length. The complexity of the utilized algorithm increased more likely polynomically, which makes it attractive for applications with a long constraint length. The algorithm requires massive parallel and fast computing, which is hard to achieve effectively using a standard digital logic. Novel floating-gate structures are used to perform highly parallel signal processing within minimal silicon area. Silicon area of a decoder having constraint length of 3 and rate 1/2 is only 950 × 450 µ m2 using 0.35 µm CMOS. Measurements show that a BER of 0.06 can be obtained at decoding speed of 1.25 MHz with a input signal having SNR of 0dB.

AB - A silicon efficient real-time approach to decode convolutional codes is presented. The algorithm is a special recurrent neural network, which needs no supervision. A standard solution for the convolutional decoding has been the Viterbi algorithm, which is an optimal solution. The complexity of a Viterbi decoder increases exponentially as a function of the constraint length. The complexity of the utilized algorithm increased more likely polynomically, which makes it attractive for applications with a long constraint length. The algorithm requires massive parallel and fast computing, which is hard to achieve effectively using a standard digital logic. Novel floating-gate structures are used to perform highly parallel signal processing within minimal silicon area. Silicon area of a decoder having constraint length of 3 and rate 1/2 is only 950 × 450 µ m2 using 0.35 µm CMOS. Measurements show that a BER of 0.06 can be obtained at decoding speed of 1.25 MHz with a input signal having SNR of 0dB.

M3 - Conference article in proceedings

SN - 2-914601-00-X

SP - 452

EP - 455

BT - Proceedings of the 27th European Solid-State Circuits Conference

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - 27th European Solid-State Circuits Conference, ESSCIRC 2001

Y2 - 18 September 2001 through 20 September 2001

ER -

A silicon efficient high speed L=3 rate 1/2 convolutional decoder using recurrent neural networks

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