A single clocked adiabatic static logic: A proposal for digital low power applications

Jouko Marjonen, Markku Åberg

Research output: Contribution to journalArticleScientificpeer-review

17 Citations (Scopus)

Abstract

A modified method to construct adiabatic logic is introduced. Advantages of this circuitry over most of the previous ones is that logic behaves in a static mode. In the present research the applicability of a one-phase power clock was studied. The functionality was guaranteed by having the power source frequency much higher than the logic frequency. The new logic gates do not differ much from any standard CMOS logic gates. The only difference is the use of diodes to form logical ‘1’ and ‘0’ states. The static nature of the introduced logic family makes possible to apply the charge recycling technic to other more complex digital circuits and systems. In measurements 77% power saving was achieved compared to a conventional CMOS logic.
Original languageEnglish
Pages (from-to)253-268
Number of pages16
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Volume27
Issue number3
DOIs
Publication statusPublished - 2001
MoE publication typeA1 Journal article-refereed

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Logic gates
Logic
Digital circuits
Recycling
Clocks
Diodes
Digital Circuits
Power Saving
Diode
Charge

Cite this

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title = "A single clocked adiabatic static logic: A proposal for digital low power applications",
abstract = "A modified method to construct adiabatic logic is introduced. Advantages of this circuitry over most of the previous ones is that logic behaves in a static mode. In the present research the applicability of a one-phase power clock was studied. The functionality was guaranteed by having the power source frequency much higher than the logic frequency. The new logic gates do not differ much from any standard CMOS logic gates. The only difference is the use of diodes to form logical ‘1’ and ‘0’ states. The static nature of the introduced logic family makes possible to apply the charge recycling technic to other more complex digital circuits and systems. In measurements 77{\%} power saving was achieved compared to a conventional CMOS logic.",
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A single clocked adiabatic static logic : A proposal for digital low power applications. / Marjonen, Jouko; Åberg, Markku.

In: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Vol. 27, No. 3, 2001, p. 253-268.

Research output: Contribution to journalArticleScientificpeer-review

TY - JOUR

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T2 - A proposal for digital low power applications

AU - Marjonen, Jouko

AU - Åberg, Markku

PY - 2001

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N2 - A modified method to construct adiabatic logic is introduced. Advantages of this circuitry over most of the previous ones is that logic behaves in a static mode. In the present research the applicability of a one-phase power clock was studied. The functionality was guaranteed by having the power source frequency much higher than the logic frequency. The new logic gates do not differ much from any standard CMOS logic gates. The only difference is the use of diodes to form logical ‘1’ and ‘0’ states. The static nature of the introduced logic family makes possible to apply the charge recycling technic to other more complex digital circuits and systems. In measurements 77% power saving was achieved compared to a conventional CMOS logic.

AB - A modified method to construct adiabatic logic is introduced. Advantages of this circuitry over most of the previous ones is that logic behaves in a static mode. In the present research the applicability of a one-phase power clock was studied. The functionality was guaranteed by having the power source frequency much higher than the logic frequency. The new logic gates do not differ much from any standard CMOS logic gates. The only difference is the use of diodes to form logical ‘1’ and ‘0’ states. The static nature of the introduced logic family makes possible to apply the charge recycling technic to other more complex digital circuits and systems. In measurements 77% power saving was achieved compared to a conventional CMOS logic.

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DO - 10.1023/A:1008143316204

M3 - Article

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SP - 253

EP - 268

JO - Journal of Signal Processing Systems

JF - Journal of Signal Processing Systems

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