A temperature and process compensation circuit for resistive-based in-memory computing arrays

Dipesh C. Monga; Omar Numan; Martin Andraud; Kari Halonen

doi:10.1109/ISCAS46773.2023.10181619

A temperature and process compensation circuit for resistive-based in-memory computing arrays

Dipesh C. Monga
, Omar Numan
, Martin Andraud
, Kari Halonen

Not published at VTT

Aalto University

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

6 Citations (Scopus)

Abstract

In-Memory Computing (IMC) architectures promise increased energy-efficiency for embedded artificial intelligence. Many IMC circuits rely on analog computation, which is more sensitive to process and temperature variations than digital. Thus, maintaining a suitable computation accuracy may require process and temperature compensation. Focusing on resistive-based IMC architectures, we propose an ultra-low power circuit to compensate for the temperature and process-based non-linearities of resistive computing elements. The proposed circuit, implemented in 65 nm CMOS can provide a temperature coefficient between 10 and 1938 ppm/°C for a wide temperature range (-40°C to 80°C) and output current range (few pA up to 600 nA) at 1.2 V operating voltage. Used in a resistive IMC array, the variation of output currents from each multiply-accumulate (MAC) operation can be reduced by up to 84% to maintain computation accuracy across process and temperature variations.

Original language	English
Title of host publication	2023 IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher	IEEE Institute of Electrical and Electronic Engineers
ISBN (Electronic)	978-1-6654-5109-3
DOIs	https://doi.org/10.1109/ISCAS46773.2023.10181619
Publication status	Published - 2023
MoE publication type	A4 Article in a conference publication
Event	56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 - Monterey, United States Duration: 21 May 2023 → 25 May 2023

Conference

Conference	56th IEEE International Symposium on Circuits and Systems, ISCAS 2023
Country/Territory	United States
City	Monterey
Period	21/05/23 → 25/05/23

Funding

ACKNOWLEDGMENTS This work is supported by Academy of Finland projects EHIR (grant 13334487) and WHISTLE (grant 332218)

Keywords

In-memory computing
process compensation
Resistive random access memory
Thermal compensation
ultra-low power
variable temperature coefficient

Access to Document

10.1109/ISCAS46773.2023.10181619

Cite this

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title = "A temperature and process compensation circuit for resistive-based in-memory computing arrays",

abstract = "In-Memory Computing (IMC) architectures promise increased energy-efficiency for embedded artificial intelligence. Many IMC circuits rely on analog computation, which is more sensitive to process and temperature variations than digital. Thus, maintaining a suitable computation accuracy may require process and temperature compensation. Focusing on resistive-based IMC architectures, we propose an ultra-low power circuit to compensate for the temperature and process-based non-linearities of resistive computing elements. The proposed circuit, implemented in 65 nm CMOS can provide a temperature coefficient between 10 and 1938 ppm/°C for a wide temperature range (-40°C to 80°C) and output current range (few pA up to 600 nA) at 1.2 V operating voltage. Used in a resistive IMC array, the variation of output currents from each multiply-accumulate (MAC) operation can be reduced by up to 84\% to maintain computation accuracy across process and temperature variations.",

keywords = "In-memory computing, process compensation, Resistive random access memory, Thermal compensation, ultra-low power, variable temperature coefficient",

author = "Monga, \{Dipesh C.\} and Omar Numan and Martin Andraud and Kari Halonen",

year = "2023",

doi = "10.1109/ISCAS46773.2023.10181619",

language = "English",

booktitle = "2023 IEEE International Symposium on Circuits and Systems (ISCAS)",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

note = "56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 ; Conference date: 21-05-2023 Through 25-05-2023",

}

Monga, DC , Numan, O, Andraud, M & Halonen, K 2023, A temperature and process compensation circuit for resistive-based in-memory computing arrays. in 2023 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE Institute of Electrical and Electronic Engineers, 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, United States, 21/05/23. https://doi.org/10.1109/ISCAS46773.2023.10181619

A temperature and process compensation circuit for resistive-based in-memory computing arrays. / Monga, Dipesh C.; Numan, Omar; Andraud, Martin et al.
2023 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE Institute of Electrical and Electronic Engineers, 2023.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - A temperature and process compensation circuit for resistive-based in-memory computing arrays

AU - Monga, Dipesh C.

AU - Numan, Omar

AU - Andraud, Martin

AU - Halonen, Kari

PY - 2023

Y1 - 2023

N2 - In-Memory Computing (IMC) architectures promise increased energy-efficiency for embedded artificial intelligence. Many IMC circuits rely on analog computation, which is more sensitive to process and temperature variations than digital. Thus, maintaining a suitable computation accuracy may require process and temperature compensation. Focusing on resistive-based IMC architectures, we propose an ultra-low power circuit to compensate for the temperature and process-based non-linearities of resistive computing elements. The proposed circuit, implemented in 65 nm CMOS can provide a temperature coefficient between 10 and 1938 ppm/°C for a wide temperature range (-40°C to 80°C) and output current range (few pA up to 600 nA) at 1.2 V operating voltage. Used in a resistive IMC array, the variation of output currents from each multiply-accumulate (MAC) operation can be reduced by up to 84% to maintain computation accuracy across process and temperature variations.

AB - In-Memory Computing (IMC) architectures promise increased energy-efficiency for embedded artificial intelligence. Many IMC circuits rely on analog computation, which is more sensitive to process and temperature variations than digital. Thus, maintaining a suitable computation accuracy may require process and temperature compensation. Focusing on resistive-based IMC architectures, we propose an ultra-low power circuit to compensate for the temperature and process-based non-linearities of resistive computing elements. The proposed circuit, implemented in 65 nm CMOS can provide a temperature coefficient between 10 and 1938 ppm/°C for a wide temperature range (-40°C to 80°C) and output current range (few pA up to 600 nA) at 1.2 V operating voltage. Used in a resistive IMC array, the variation of output currents from each multiply-accumulate (MAC) operation can be reduced by up to 84% to maintain computation accuracy across process and temperature variations.

KW - In-memory computing

KW - process compensation

KW - Resistive random access memory

KW - Thermal compensation

KW - ultra-low power

KW - variable temperature coefficient

UR - https://www.scopus.com/pages/publications/85167700583

U2 - 10.1109/ISCAS46773.2023.10181619

DO - 10.1109/ISCAS46773.2023.10181619

M3 - Conference article in proceedings

AN - SCOPUS:85167700583

BT - 2023 IEEE International Symposium on Circuits and Systems (ISCAS)

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023

Y2 - 21 May 2023 through 25 May 2023

ER -

A temperature and process compensation circuit for resistive-based in-memory computing arrays

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