Subthreshold source-coupled logic (STSCL) has been recently shown to be an advantageous logic style for ultra-low power applications. In the subthreshold region, STSCL provides improved power-delay performance and increased robustness over static CMOS logic. In this paper, we present a new timing error detection (TED) latch, or (TEDsc), which uses STSCL for detecting timing errors while using static CMOS logic for latching data. This allows for TEDsc to be easily integrated into a TED pipeline with static CMOS logic. At Vdd=300 mV, TEDsc consumes 40% less power than an all-static CMOS subthreshold-capable TED latch.
|Title of host publication||6th Conference on Ph.D. Research in Microelectronics & Electronics|
|Place of Publication||Piscataway, NJ, USA|
|Publisher||IEEE Institute of Electrical and Electronic Engineers|
|ISBN (Electronic)||978-3-9813-7540-4, 978-3-9813754-1-1|
|Publication status||Published - 27 Sep 2010|
|MoE publication type||A4 Article in a conference publication|
|Event||6th Conference on Ph.D. Research in Microelectronics & Electronics, PRIME 2010 - Berlin, Germany|
Duration: 18 Jun 2010 → 21 Jun 2010
Conference number: 6
|Conference||6th Conference on Ph.D. Research in Microelectronics & Electronics, PRIME 2010|
|Abbreviated title||PRIME 2010|
|Period||18/06/10 → 21/06/10|
- timing error detection
Turnquist, M. J., Laulajainen, E., Mäkipää, J., & Koskinen, L. (2010). A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic. In 6th Conference on Ph.D. Research in Microelectronics & Electronics IEEE Institute of Electrical and Electronic Engineers .