A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic

Matthew J. Turnquist, Erkka Laulajainen, Jani Mäkipää, Lauri Koskinen

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

3 Citations (Scopus)

Abstract

Subthreshold source-coupled logic (STSCL) has been recently shown to be an advantageous logic style for ultra-low power applications. In the subthreshold region, STSCL provides improved power-delay performance and increased robustness over static CMOS logic. In this paper, we present a new timing error detection (TED) latch, or (TEDsc), which uses STSCL for detecting timing errors while using static CMOS logic for latching data. This allows for TEDsc to be easily integrated into a TED pipeline with static CMOS logic. At Vdd=300 mV, TEDsc consumes 40% less power than an all-static CMOS subthreshold-capable TED latch.
Original languageEnglish
Title of host publication6th Conference on Ph.D. Research in Microelectronics & Electronics
Place of PublicationPiscataway, NJ, USA
PublisherInstitute of Electrical and Electronic Engineers IEEE
ISBN (Electronic)978-3-9813-7540-4, 978-3-9813754-1-1
ISBN (Print)978-1-4244-7905-4
Publication statusPublished - 27 Sep 2010
MoE publication typeA4 Article in a conference publication
Event6th Conference on Ph.D. Research in Microelectronics & Electronics, PRIME 2010 - Berlin, Germany
Duration: 18 Jun 201021 Jun 2010
Conference number: 6

Conference

Conference6th Conference on Ph.D. Research in Microelectronics & Electronics, PRIME 2010
Abbreviated titlePRIME 2010
CountryGermany
CityBerlin
Period18/06/1021/06/10

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Keywords

  • timing error detection
  • subtreshold

Cite this

Turnquist, M. J., Laulajainen, E., Mäkipää, J., & Koskinen, L. (2010). A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic. In 6th Conference on Ph.D. Research in Microelectronics & Electronics Piscataway, NJ, USA: Institute of Electrical and Electronic Engineers IEEE.
Turnquist, Matthew J. ; Laulajainen, Erkka ; Mäkipää, Jani ; Koskinen, Lauri. / A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic. 6th Conference on Ph.D. Research in Microelectronics & Electronics. Piscataway, NJ, USA : Institute of Electrical and Electronic Engineers IEEE, 2010.
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title = "A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic",
abstract = "Subthreshold source-coupled logic (STSCL) has been recently shown to be an advantageous logic style for ultra-low power applications. In the subthreshold region, STSCL provides improved power-delay performance and increased robustness over static CMOS logic. In this paper, we present a new timing error detection (TED) latch, or (TEDsc), which uses STSCL for detecting timing errors while using static CMOS logic for latching data. This allows for TEDsc to be easily integrated into a TED pipeline with static CMOS logic. At Vdd=300 mV, TEDsc consumes 40{\%} less power than an all-static CMOS subthreshold-capable TED latch.",
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Turnquist, MJ, Laulajainen, E, Mäkipää, J & Koskinen, L 2010, A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic. in 6th Conference on Ph.D. Research in Microelectronics & Electronics. Institute of Electrical and Electronic Engineers IEEE, Piscataway, NJ, USA, 6th Conference on Ph.D. Research in Microelectronics & Electronics, PRIME 2010, Berlin, Germany, 18/06/10.

A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic. / Turnquist, Matthew J.; Laulajainen, Erkka; Mäkipää, Jani; Koskinen, Lauri.

6th Conference on Ph.D. Research in Microelectronics & Electronics. Piscataway, NJ, USA : Institute of Electrical and Electronic Engineers IEEE, 2010.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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T1 - A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic

AU - Turnquist, Matthew J.

AU - Laulajainen, Erkka

AU - Mäkipää, Jani

AU - Koskinen, Lauri

N1 - Project code: 25726

PY - 2010/9/27

Y1 - 2010/9/27

N2 - Subthreshold source-coupled logic (STSCL) has been recently shown to be an advantageous logic style for ultra-low power applications. In the subthreshold region, STSCL provides improved power-delay performance and increased robustness over static CMOS logic. In this paper, we present a new timing error detection (TED) latch, or (TEDsc), which uses STSCL for detecting timing errors while using static CMOS logic for latching data. This allows for TEDsc to be easily integrated into a TED pipeline with static CMOS logic. At Vdd=300 mV, TEDsc consumes 40% less power than an all-static CMOS subthreshold-capable TED latch.

AB - Subthreshold source-coupled logic (STSCL) has been recently shown to be an advantageous logic style for ultra-low power applications. In the subthreshold region, STSCL provides improved power-delay performance and increased robustness over static CMOS logic. In this paper, we present a new timing error detection (TED) latch, or (TEDsc), which uses STSCL for detecting timing errors while using static CMOS logic for latching data. This allows for TEDsc to be easily integrated into a TED pipeline with static CMOS logic. At Vdd=300 mV, TEDsc consumes 40% less power than an all-static CMOS subthreshold-capable TED latch.

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KW - subtreshold

M3 - Conference article in proceedings

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BT - 6th Conference on Ph.D. Research in Microelectronics & Electronics

PB - Institute of Electrical and Electronic Engineers IEEE

CY - Piscataway, NJ, USA

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Turnquist MJ, Laulajainen E, Mäkipää J, Koskinen L. A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic. In 6th Conference on Ph.D. Research in Microelectronics & Electronics. Piscataway, NJ, USA: Institute of Electrical and Electronic Engineers IEEE. 2010