A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic

Matthew J. Turnquist; Erkka Laulajainen; Jani Mäkipää; Lauri Koskinen

A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic

Matthew J. Turnquist, Erkka Laulajainen, Jani Mäkipää, Lauri Koskinen

VTT Technical Research Centre of Finland

Aalto University

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

3 Citations (Scopus)

Abstract

Subthreshold source-coupled logic (STSCL) has been recently shown to be an advantageous logic style for ultra-low power applications. In the subthreshold region, STSCL provides improved power-delay performance and increased robustness over static CMOS logic. In this paper, we present a new timing error detection (TED) latch, or (TEDsc), which uses STSCL for detecting timing errors while using static CMOS logic for latching data. This allows for TEDsc to be easily integrated into a TED pipeline with static CMOS logic. At V_dd=300 mV, TEDsc consumes 40% less power than an all-static CMOS subthreshold-capable TED latch.

Original language	English
Title of host publication	6th Conference on Ph.D. Research in Microelectronics & Electronics
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE Institute of Electrical and Electronic Engineers
ISBN (Electronic)	978-3-9813-7540-4, 978-3-9813754-1-1
ISBN (Print)	978-1-4244-7905-4
Publication status	Published - 27 Sept 2010
MoE publication type	A4 Article in a conference publication
Event	6th Conference on Ph.D. Research in Microelectronics & Electronics, PRIME 2010 - Berlin, Germany Duration: 18 Jun 2010 → 21 Jun 2010 Conference number: 6

Conference

Conference	6th Conference on Ph.D. Research in Microelectronics & Electronics, PRIME 2010
Abbreviated title	PRIME 2010
Country/Territory	Germany
City	Berlin
Period	18/06/10 → 21/06/10

Keywords

timing error detection
subtreshold

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Cite this

@inproceedings{efe9dcadb8fc4f8aa72c164f7d57f1f2,

title = "A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic",

abstract = "Subthreshold source-coupled logic (STSCL) has been recently shown to be an advantageous logic style for ultra-low power applications. In the subthreshold region, STSCL provides improved power-delay performance and increased robustness over static CMOS logic. In this paper, we present a new timing error detection (TED) latch, or (TEDsc), which uses STSCL for detecting timing errors while using static CMOS logic for latching data. This allows for TEDsc to be easily integrated into a TED pipeline with static CMOS logic. At Vdd=300 mV, TEDsc consumes 40% less power than an all-static CMOS subthreshold-capable TED latch.",

keywords = "timing error detection, subtreshold",

author = "Turnquist, {Matthew J.} and Erkka Laulajainen and Jani M{\"a}kip{\"a}{\"a} and Lauri Koskinen",

note = "Project code: 25726; 6th Conference on Ph.D. Research in Microelectronics & Electronics, PRIME 2010, PRIME 2010 ; Conference date: 18-06-2010 Through 21-06-2010",

year = "2010",

month = sep,

day = "27",

language = "English",

isbn = "978-1-4244-7905-4",

booktitle = "6th Conference on Ph.D. Research in Microelectronics & Electronics",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

}

Turnquist, MJ, Laulajainen, E, Mäkipää, J & Koskinen, L 2010, A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic. in 6th Conference on Ph.D. Research in Microelectronics & Electronics. IEEE Institute of Electrical and Electronic Engineers, Piscataway, NJ, USA, 6th Conference on Ph.D. Research in Microelectronics & Electronics, PRIME 2010, Berlin, Germany, 18/06/10. <https://ieeexplore.ieee.org/document/5587177/authors#authors>

A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic. / Turnquist, Matthew J.; Laulajainen, Erkka; Mäkipää, Jani et al.
6th Conference on Ph.D. Research in Microelectronics & Electronics. Piscataway, NJ, USA: IEEE Institute of Electrical and Electronic Engineers, 2010.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic

AU - Turnquist, Matthew J.

AU - Laulajainen, Erkka

AU - Mäkipää, Jani

AU - Koskinen, Lauri

N1 - Conference code: 6

PY - 2010/9/27

Y1 - 2010/9/27

N2 - Subthreshold source-coupled logic (STSCL) has been recently shown to be an advantageous logic style for ultra-low power applications. In the subthreshold region, STSCL provides improved power-delay performance and increased robustness over static CMOS logic. In this paper, we present a new timing error detection (TED) latch, or (TEDsc), which uses STSCL for detecting timing errors while using static CMOS logic for latching data. This allows for TEDsc to be easily integrated into a TED pipeline with static CMOS logic. At Vdd=300 mV, TEDsc consumes 40% less power than an all-static CMOS subthreshold-capable TED latch.

AB - Subthreshold source-coupled logic (STSCL) has been recently shown to be an advantageous logic style for ultra-low power applications. In the subthreshold region, STSCL provides improved power-delay performance and increased robustness over static CMOS logic. In this paper, we present a new timing error detection (TED) latch, or (TEDsc), which uses STSCL for detecting timing errors while using static CMOS logic for latching data. This allows for TEDsc to be easily integrated into a TED pipeline with static CMOS logic. At Vdd=300 mV, TEDsc consumes 40% less power than an all-static CMOS subthreshold-capable TED latch.

KW - timing error detection

KW - subtreshold

M3 - Conference article in proceedings

SN - 978-1-4244-7905-4

BT - 6th Conference on Ph.D. Research in Microelectronics & Electronics

PB - IEEE Institute of Electrical and Electronic Engineers

CY - Piscataway, NJ, USA

T2 - 6th Conference on Ph.D. Research in Microelectronics & Electronics, PRIME 2010

Y2 - 18 June 2010 through 21 June 2010

ER -

A Timing Error Detection Latch Using Subthreshold Source-Coupled Logic

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Keywords

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