A VHDL simulator in a co-verification environment

Master's thesis

Klaus Melakari

Research output: ThesisMaster's thesisTheses

Abstract

In this work, methods and tools are developed for the integration of a VHDL simulation environment into the Modelling and Simulation Environment (MSE) of the ESPRIT project EP20576 (OMI/TOOLS). The MSE is a co-verification environment for the verification of mixed hardware/software systems that eventually can be implemented as system-chips. System-chips are integrated circuits consisting of processors, memories, software components and application specific hardware parts. The VHDL simulation environment constitutes that part of the MSE which is intended for the simulation of the hardware part in VHDL of the mixed hardware/software system. The software part is modelled in C and it is simulated by a ClearSim software simulator. In addition to simulators, the MSE contains the Graphical Model Builder, the Model Database, the InterOperation Engine and the Graphical Animator to provide means for reusability and efficient handling of the system-level issues. The contribution of this work to the MSE development is the specification, design, implementation and testing of the methods and programs that enable integration of the VHDL environment into the MSE. The integration requires an interface to the modelling and simulation backplane. The functionality of the integrated VHDL simulator was tested by simulating two hardware/software models. The results were then compared with current solutions and industrial expectations. The key result was that the MSE integrated VHDL simulator can provide the simulation of the hardware portion in the co-simulation of mixed hardware/software systems. The estimations of achievable performance assessed that the MSE, as a whole, enables much faster co-simulation than any currently existing commercial solution.
Original languageEnglish
QualificationMaster Degree
Awarding Institution
  • University of Oulu
Supervisors/Advisors
  • Kostamovaara, Juha, Supervisor, External person
  • Heusala, Hannu, Supervisor, External person
Place of PublicationEspoo
Publisher
Print ISBNs951-38-5245-8
Electronic ISBNs951-38-4246-6
Publication statusPublished - 1998
MoE publication typeG2 Master's thesis, polytechnic Master's thesis

Fingerprint

Computer hardware description languages
Simulators
Hardware
Reusability
Computer hardware
Integrated circuits
Engines
Specifications
Data storage equipment
Testing

Keywords

  • VHDL
  • simulators
  • co-simulation
  • embedded systems

Cite this

Melakari, K. (1998). A VHDL simulator in a co-verification environment: Master's thesis. Espoo: VTT Technical Research Centre of Finland.
Melakari, Klaus. / A VHDL simulator in a co-verification environment : Master's thesis. Espoo : VTT Technical Research Centre of Finland, 1998. 97 p.
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Melakari, K 1998, 'A VHDL simulator in a co-verification environment: Master's thesis', Master Degree, University of Oulu, Espoo.

A VHDL simulator in a co-verification environment : Master's thesis. / Melakari, Klaus.

Espoo : VTT Technical Research Centre of Finland, 1998. 97 p.

Research output: ThesisMaster's thesisTheses

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AB - In this work, methods and tools are developed for the integration of a VHDL simulation environment into the Modelling and Simulation Environment (MSE) of the ESPRIT project EP20576 (OMI/TOOLS). The MSE is a co-verification environment for the verification of mixed hardware/software systems that eventually can be implemented as system-chips. System-chips are integrated circuits consisting of processors, memories, software components and application specific hardware parts. The VHDL simulation environment constitutes that part of the MSE which is intended for the simulation of the hardware part in VHDL of the mixed hardware/software system. The software part is modelled in C and it is simulated by a ClearSim software simulator. In addition to simulators, the MSE contains the Graphical Model Builder, the Model Database, the InterOperation Engine and the Graphical Animator to provide means for reusability and efficient handling of the system-level issues. The contribution of this work to the MSE development is the specification, design, implementation and testing of the methods and programs that enable integration of the VHDL environment into the MSE. The integration requires an interface to the modelling and simulation backplane. The functionality of the integrated VHDL simulator was tested by simulating two hardware/software models. The results were then compared with current solutions and industrial expectations. The key result was that the MSE integrated VHDL simulator can provide the simulation of the hardware portion in the co-simulation of mixed hardware/software systems. The estimations of achievable performance assessed that the MSE, as a whole, enables much faster co-simulation than any currently existing commercial solution.

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Melakari K. A VHDL simulator in a co-verification environment: Master's thesis. Espoo: VTT Technical Research Centre of Finland, 1998. 97 p.