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A VHDL simulator in a co-verification environment: Master's thesis
Klaus Melakari
VTT Technical Research Centre of Finland
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Master's thesis
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Keyphrases
Simulation Environment
100%
Master's Thesis
100%
Verification Environment
100%
Co-verification
100%
HIL Simulation
100%
Modeling Environment
80%
Hardware Complexity
40%
Co-simulation
20%
System-on-chip
20%
System Level
10%
Software Application
10%
Integrated Circuits
10%
Software Components
10%
Graphical Models
10%
Reusability
10%
Model Builder
10%
Current Solution
10%
Work Method
10%
Backplane
10%
Achievable Performance
10%
Specification Design
10%
ESPRIT
10%
Interoperation
10%
Software Model
10%
Specification Testing
10%
Environmental Development
10%
Animator
10%
Software Simulator
10%
Model Database
10%
Application-specific Hardware
10%
Working Tools
10%
Commercial Solutions
10%
INIS
simulation
100%
environment
100%
simulators
100%
verification
100%
modeling
56%
computer codes
43%
solutions
12%
tools
6%
performance
6%
comparative evaluations
6%
levels
6%
applications
6%
interfaces
6%
implementation
6%
design
6%
testing
6%
engines
6%
specifications
6%
integrated circuits
6%
builders
6%
Computer Science
Simulation Environment
100%
Modeling and Simulation
90%
Modeling Environment
80%
Computer Hardware
70%
Software Systems
30%
Commercial Solution
10%
Achievable Performance
10%
Database Model
10%
Design Implementation
10%
Interoperation
10%
Graphical Model
10%
Software Model
10%
Software Component
10%
Software Application
10%
Integrated Circuit
10%
Engineering
Simulation Environment
100%
Modeling Environment
80%
Software Systems
30%
Methods and Tool
10%
Software Component
10%
Software Application
10%
Reusability
10%
Design Specification
10%
Software Simulator
10%
Integrated Circuit
10%