Advanced simulation environment for shared memory network-on-chips

A new class of System-on-Chips (SOC) called Network-on-Chips (NOC) has recently been proposed to solve the architectural and design complexity issues of future SOCs. The design and selection of an architecture for a NOC is, however, not a trivial task, because it requires expertise in parallel computing ranging from detailed processor microarchitectures to complex system architectures and from instruction-level parallelism (ILP) to thread-level parallelism (TLP) at various ganularities. We have developed a simulation environment called IPSMSim for evaluating parallel architectures based on a network of homogeneous computing resources and exploring the effect of architectural solutions on ILP and TLP exploitation on those architectures. IPSMSim supports currently parametric single and multithreaded processors, various interconnection topologies and memory module organizations realizing the shared memory and message passing programming models. IPSMSim has tools for compiling and loading native assembler programs, importing RISC programs as well as translating and optimizing them to native architecture, and collecting various types of execution and communication statistics. IPSMSim has been successfully applied to a number of researches ranging from microarchitecture-level to system-level evaluations.