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Alternative fabrication process for edgeless detectors on 6 in. wafers
Juha Kalliopuska
*
, Simo Eränen
, Tuula Virolainen
*
Corresponding author for this work
VTT Technical Research Centre of Finland
Research output
:
Contribution to journal
›
Article
›
Scientific
›
peer-review
13
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Keyphrases
Active Edge
100%
Breakdown Voltage
40%
Capacitance
20%
Capacitance-voltage
20%
Coupled Microstrip Lines
20%
Current-voltage
20%
DC-coupled
20%
Dead Layer
20%
Edge Distance
80%
Edgeless
60%
Edgeless Detector
100%
Electrical Characterization
20%
Fabrication Methods
100%
Fast Processes
20%
FZ Silicon
20%
High Resistivity
20%
ICP Etching
20%
Leakage Current
40%
Medipix2
20%
Microstrip
20%
Microstrip Design
20%
Microstrip Detector
40%
Pixel Detector
40%
Planarization
20%
Polysilicon
20%
Reverse Bias
40%
Silicon Wafer
20%
Slow Process
20%
Voltage Measurement
20%
Wafer
100%
Wafer Level
20%
INIS
breakdown
50%
capacitance
50%
couplings
25%
design
50%
distance
100%
etching
25%
fabrication
100%
growth
25%
layers
25%
leakage current
50%
levels
25%
silicon
25%
thickness
25%
vanadium 40
25%
voltage
50%
Engineering
Breakdown Voltage
100%
Electrical Measurement
50%
Measured Parameter
50%
Planarization
50%
Polysilicon
50%
Process Step
50%
Reverse Bias
100%
Silicon Wafer
50%
Material Science
Capacitance
100%
Electrical Resistivity
50%
Silicon Wafer
50%