Abstract
An 5.1 μW, 1.8 V, 8-bit, successive approximation (SAR) analog-to-digital converter (ADC) using 10 kHz clock was designed and fabricated in a 0.18 μm CMOS technology for passive UHF radio frequency identification (RFID) applications. The ADC utilises a resistive digital to analog converter (DAC). The ADC can operate with low power consumption. The proposed comparator with cascode active load can offer large gain and can operate at a low supply voltage. The measured total power consumption is 5.1 μW at a 10 kHz input clock with a 1.8 V single supply, and 0.5 μW with 970 mV supply.
Original language | English |
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Pages (from-to) | 389-405 |
Number of pages | 17 |
Journal | Analog Integrated Circuits and Signal Processing |
Volume | 66 |
Issue number | 3 |
DOIs | |
Publication status | Published - 2010 |
MoE publication type | A1 Journal article-refereed |
Keywords
- ADC
- Micro power
- RFID
- Wireless sensor network
- Noise