An 5.1 μW, 1.8 V, 8-bit, successive approximation (SAR) analog-to-digital converter (ADC) using 10 kHz clock was designed and fabricated in a 0.18 μm CMOS technology for passive UHF radio frequency identification (RFID) applications. The ADC utilises a resistive digital to analog converter (DAC). The ADC can operate with low power consumption. The proposed comparator with cascode active load can offer large gain and can operate at a low supply voltage. The measured total power consumption is 5.1 μW at a 10 kHz input clock with a 1.8 V single supply, and 0.5 μW with 970 mV supply.
- Micro power
- Wireless sensor network
Marjonen, J., Vermesan, O., & Rustad, H. (2010). An 8-bit, 10 kHz, 5.1 µW, 0.18 µm CMOS SAR ADC for RFID applications with sensing capabilities. Analog Integrated Circuits and Signal Processing, 66(3), 389-405. https://doi.org/10.1007/s10470-010-9527-z