An 8-bit and 10-bit low power high speed neuron MOS digital-to-analog converter in 0.04 mm2

Arto Rantala; Pekka Kuivalainen; Markku Åberg

An 8-bit and 10-bit low power high speed neuron MOS digital-to-analog converter in 0.04 mm²

Arto Rantala, Pekka Kuivalainen, Markku Åberg

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

Abstract

Digital-to-analog converts utilizing neuron MOS-transistors were designed. A 8-bit version is implemented with only one neuron MOS-transistor and 8 capacitors. The silicon area of the D/A converter is only 0.04 mm ² and the power consumption is 7.5 mW at 200 MS/s. The measured DNL is 0.23 LSB and INL 0.47 LSB. An enhanced version is also proposed. The silicon area of the enhanced circuit is smaller while the number of the bits can be increased to 10. A method to increase the linearity of the proposed D/A converters is presented.

Original language	English
Title of host publication	Proceedings of the 25th European Solid-State Circuits Conference
Publisher	Editions Frontières
Pages	310-314
ISBN (Print)	2-86332-246-X
Publication status	Published - 1999
MoE publication type	A4 Article in a conference publication
Event	25th European Solid-State Circuits Conference, ESSCIRC '99 - Duisburg, Germany Duration: 21 Sept 1999 → 23 Sept 1999

Conference

Conference	25th European Solid-State Circuits Conference, ESSCIRC '99
Country/Territory	Germany
City	Duisburg
Period	21/09/99 → 23/09/99

Access to Document

https://ieeexplore.ieee.org/document/1471158

Cite this

@inproceedings{4cb3d15f08ab4fc2a3cf7f83458e2c5d,

title = "An 8-bit and 10-bit low power high speed neuron MOS digital-to-analog converter in 0.04 mm2",

abstract = "Digital-to-analog converts utilizing neuron MOS-transistors were designed. A 8-bit version is implemented with only one neuron MOS-transistor and 8 capacitors. The silicon area of the D/A converter is only 0.04 mm 2 and the power consumption is 7.5 mW at 200 MS/s. The measured DNL is 0.23 LSB and INL 0.47 LSB. An enhanced version is also proposed. The silicon area of the enhanced circuit is smaller while the number of the bits can be increased to 10. A method to increase the linearity of the proposed D/A converters is presented.",

author = "Arto Rantala and Pekka Kuivalainen and Markku {\AA}berg",

year = "1999",

language = "English",

isbn = "2-86332-246-X",

pages = "310--314",

booktitle = "Proceedings of the 25th European Solid-State Circuits Conference",

publisher = "Editions Fronti{\`e}res",

address = "France",

note = "25th European Solid-State Circuits Conference, ESSCIRC '99 ; Conference date: 21-09-1999 Through 23-09-1999",

}

Rantala, A, Kuivalainen, P & Åberg, M 1999, An 8-bit and 10-bit low power high speed neuron MOS digital-to-analog converter in 0.04 mm². in Proceedings of the 25th European Solid-State Circuits Conference. Editions Frontières, pp. 310-314, 25th European Solid-State Circuits Conference, ESSCIRC '99, Duisburg, North Rhine-Westphalia, Germany, 21/09/99. <https://ieeexplore.ieee.org/document/1471158>

An 8-bit and 10-bit low power high speed neuron MOS digital-to-analog converter in 0.04 mm². / Rantala, Arto; Kuivalainen, Pekka; Åberg, Markku.
Proceedings of the 25th European Solid-State Circuits Conference. Editions Frontières, 1999. p. 310-314.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - An 8-bit and 10-bit low power high speed neuron MOS digital-to-analog converter in 0.04 mm2

AU - Rantala, Arto

AU - Kuivalainen, Pekka

AU - Åberg, Markku

PY - 1999

Y1 - 1999

N2 - Digital-to-analog converts utilizing neuron MOS-transistors were designed. A 8-bit version is implemented with only one neuron MOS-transistor and 8 capacitors. The silicon area of the D/A converter is only 0.04 mm 2 and the power consumption is 7.5 mW at 200 MS/s. The measured DNL is 0.23 LSB and INL 0.47 LSB. An enhanced version is also proposed. The silicon area of the enhanced circuit is smaller while the number of the bits can be increased to 10. A method to increase the linearity of the proposed D/A converters is presented.

AB - Digital-to-analog converts utilizing neuron MOS-transistors were designed. A 8-bit version is implemented with only one neuron MOS-transistor and 8 capacitors. The silicon area of the D/A converter is only 0.04 mm 2 and the power consumption is 7.5 mW at 200 MS/s. The measured DNL is 0.23 LSB and INL 0.47 LSB. An enhanced version is also proposed. The silicon area of the enhanced circuit is smaller while the number of the bits can be increased to 10. A method to increase the linearity of the proposed D/A converters is presented.

M3 - Conference article in proceedings

SN - 2-86332-246-X

SP - 310

EP - 314

BT - Proceedings of the 25th European Solid-State Circuits Conference

PB - Editions Frontières

T2 - 25th European Solid-State Circuits Conference, ESSCIRC '99

Y2 - 21 September 1999 through 23 September 1999