Analysis of transport triggered architectures in general purpose computing

Martti Forsell

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review


    As superscalar processors are becoming more and more complex due to dynamic scheduling of instructions during execution, simpler instruction-level parallel approaches, e.g. very long instruction word (VLIW) architectures using static compile time scheduling have been considered. A rather new variant of VLIW is the transport triggered architecture (TTA), which provides programmable forwarding network and is programmed by describing data transports between functional units rather than just operations of functional units. TTAs provide means to minimize the traffic going through the forwarding network as well as commit software controlled forwarding, operand sharing, and dead result move elimination. In this paper we analytically study the capabilities of two different representatives of TTAs in general purpose computing in both single processor and multiprocessor setups. We compare the execution time of a parametric benchmark program and roughly estimate wiring area required by the forwarding network against those in the best known operation triggered architectures having the equal processing resources. The results are interesting: TTAs provide less performance than the other measured processors, but also their forwarding network seems to be remarkably smaller than in the other processors. Thus, TTAs seem to suit better for embedded computing than for general purpose computing.
    Original languageEnglish
    Title of host publicationProceedings of the 21st IEEE Norchip Conference
    Subtitle of host publicationRiga, Latvia, 10-11 November 2003
    Publication statusPublished - 2003
    MoE publication typeA4 Article in a conference publication


    • Transport triggered architecture
    • general purpose computing
    • performance model
    • area model


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