Analyzing transport and MAC layer in system-level performance simulation

Subayal Khan, Jukka Saastamoinen, Mikko Majanen, Jyrki Huusko, Jari Nurmi

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    4 Citations (Scopus)

    Abstract

    The modern mobile embedded devices support complex distributed applications via heterogeneous multi-core platforms. For the successful deployment of these applications, the scalability and performance analysis must be performed at all the layers of OSI model. This helps to identify the potential bottlenecks at different layers to perform the necessary optimizations. To achieve this goal, a framework is needed which accurately models the functionalities at different layers. The technical contributions described in this article include the extensions of ABstract inStruction wOrkLoad & execUtion plaTform based performance simulation (ABSOLUT) for the performance and scalability analysis of Transport and Medium Access Control (MAC) layers in the system level performance simulation. The article elaborates the design accuracy of the modeled components and their application in the context of M3 (multi-device, multi-vendor, multi-domain), which is a tri-layered conceptual interoperability architecture for embedded devices. These extensions pave the way towards the full coverage of the OSI model in the system-level performance simulation of distributed embedded systems. The network simulators for example ns-2, OMNeT++ and OPNET though provide detailed models of transport and MAC protocols but do not provide any framework such that these models can be used by the application workload models to mimic the real world use-cases. Also these models do not model the execution workload of these protocols on a particular execution platform and hence cannot be used in the architectural exploration of distributed embedded systems.
    Original languageEnglish
    Title of host publication2011 International Symposium on System on Chip (SoC)
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Number of pages8
    ISBN (Electronic)978-1-4577-0672-1, 978-1-4577-0670-1
    ISBN (Print)978-1-4577-0671-4
    DOIs
    Publication statusPublished - 2011
    MoE publication typeNot Eligible
    Event2011 International Symposium on System on Chip, SoC 2011 - Tampere, Finland
    Duration: 31 Oct 20112 Nov 2011

    Conference

    Conference2011 International Symposium on System on Chip, SoC 2011
    Abbreviated titleSoC 2011
    Country/TerritoryFinland
    CityTampere
    Period31/10/112/11/11

    Keywords

    • MAC
    • transport
    • ABSOLUT
    • OMNeT++
    • ns-2

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