Abstract
A processor architecture arrangement for emulated shared memory (ESM) architectures, comprises a number of, preferably a plurality of, multi-threaded processors each provided with interleaved inter-thread pipeline, wherein the pipeline comprises a plurality of functional units arranged in series for executing arithmetic, logical and optionally further operations on data, wherein one or more functional units of lower latency are positioned prior to the memory access segment in said pipeline and one or more long latency units (LLU) for executing more complex operations associated with longer latency are positioned operatively in parallel with the memory access segment. In some embodiments, the pipeline may contain multiple branches in parallel with the memory access segment, each branch containing at least one long latency unit.
Patent family as of 21.10.2021
CN106030517 A 20161012 CN201480070278 20141216
CN106030517 B 20200228 CN201480070278 20141216
DE602013061739 D1 20191107 DE201360061739T 20131219
EP2887207 A1 20150624 EP20130198516 20131219
EP2887207 B1 20191016 EP20130198516 20131219
JP2017500657 T2 20170105 JP20160541138T 20141216
JP6568859 B2 20190828 JP20160541138T 20141216
KR102269157 B1 20210624 KR20167019720 20141216
KR20170013196 A 20170206 KR20167019720 20141216
US10127048 BB 20181113 US20140105583 20141216
US2016314001 AA 20161027 US20140105583 20141216
WO15092131 A1 20150625 WO2014FI51002 20141216
Link to current patent family on right
| Original language | English |
|---|---|
| Patent number | EP2887207 |
| IPC | G06F 9/ 38 A I |
| Priority date | 19/12/13 |
| Publication status | Published - 24 Jun 2015 |
| MoE publication type | H1 Granted patent |