Automatic synthesis of structural HDL descriptions from graphic specification of embedded asics

Auli Reinikka; Antti Auer; Ari Okkonen

doi:10.1016/0165-6074(89)90094-X

Automatic synthesis of structural HDL descriptions from graphic specification of embedded asics

Auli Reinikka, Antti Auer, Ari Okkonen

VTT Technical Research Centre of Finland

Research output: Contribution to journal › Article › Scientific › peer-review

1 Citation (Scopus)

Abstract

The complex and time consuming design process of ASICs causes error-prone design steps and requires highly skilled personnel. We have chosen the automation of logic design to reduce these problems. The presented compiler generates a full structural description of a circuit directly from high-level formal behavioural specification. The compiler is based on transformation rules from graphic behavioural specification to structural architecture. This paper outlines the architectural principles to implement SOKRATES-SA models using ASIC technology and a new formal approach to fast VLSI design.

Original language	English
Pages (from-to)	473-478
Journal	Microprocessing and Microprogramming
Volume	27
Issue number	1-5
DOIs	https://doi.org/10.1016/0165-6074(89)90094-X
Publication status	Published - 1989
MoE publication type	A1 Journal article-refereed

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10.1016/0165-6074(89)90094-X

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abstract = "The complex and time consuming design process of ASICs causes error-prone design steps and requires highly skilled personnel. We have chosen the automation of logic design to reduce these problems. The presented compiler generates a full structural description of a circuit directly from high-level formal behavioural specification. The compiler is based on transformation rules from graphic behavioural specification to structural architecture. This paper outlines the architectural principles to implement SOKRATES-SA models using ASIC technology and a new formal approach to fast VLSI design.",

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AU - Okkonen, Ari

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AB - The complex and time consuming design process of ASICs causes error-prone design steps and requires highly skilled personnel. We have chosen the automation of logic design to reduce these problems. The presented compiler generates a full structural description of a circuit directly from high-level formal behavioural specification. The compiler is based on transformation rules from graphic behavioural specification to structural architecture. This paper outlines the architectural principles to implement SOKRATES-SA models using ASIC technology and a new formal approach to fast VLSI design.

U2 - 10.1016/0165-6074(89)90094-X

DO - 10.1016/0165-6074(89)90094-X

M3 - Article

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SP - 473

EP - 478

JO - Microprocessing and Microprogramming

JF - Microprocessing and Microprogramming

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ER -

Automatic synthesis of structural HDL descriptions from graphic specification of embedded asics

Abstract

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