Automatic synthesis of structural HDL descriptions from graphic specification of embedded asics

The complex and time consuming design process of ASICs causes error-prone design steps and requires highly skilled personnel. We have chosen the automation of logic design to reduce these problems. The presented compiler generates a full structural description of a circuit directly from high-level formal behavioural specification. The compiler is based on transformation rules from graphic behavioural specification to structural architecture. This paper outlines the architectural principles to implement SOKRATES-SA models using ASIC technology and a new formal approach to fast VLSI design.