Cacheless instruction fetch mechanism for multithreaded processors

The speed difference between processors and memories has become to one of the biggest problem in designing memory systems. While this primarily limits fast sequential access to data in memory it also sets constraints to efficient instruction fetch. In computers using single threaded processors this latter problem has traditionally been partially solved by using instruction caches, but in fast multithreaded processors supporting a large number of threads the problem is more difficult, because each thread can execute the program from an unique address (MIMD-style) or all threads can just access the same location synchronously (SIMD-style). In this paper we propose two cacheless instruction fetch mechanisms for multithreaded processors composed of an interthread pipelined instruction fetch unit and a banked instruction memory module using randomized hashing, combining and partitioning. The proposed mechanisms along with a two reference mechanisms based on direct mapped and T-way set associative caching are evaluated in a T-threaded case by simulations. According to our evaluation the proposed mechanisms solve efficiently the speed difference problem and provide clearly better performance than the reference solutions.