Challenges of parallel processor design

Martti Forsell, Ville Leppänen, Martti Penttonen

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    Abstract

    While processor speeds have grown, also the gap between the speed of processing and the speed of accessing data has grown. Therefore the speed of the processor cannot be used. As a reaction, processor industry has started to build more processor cores on a chip, but there is no easy way to utilize multiple processors. In this work we study alternative multicore processor designs that could efficiently run parallel programs.
    Original languageEnglish
    Title of host publicationProceedings of AMICT'2009
    Subtitle of host publicationAnnual International Workshop on Advances in Methods of Information and Communication Technology
    EditorsJussi Kangasharju, Yury A. Bogoyavlenskiy
    PublisherPetrozavodskij gosudarstvenny`j universitet
    Pages75-87
    Publication statusPublished - 2009
    MoE publication typeA4 Article in a conference publication
    EventAnnual International Workshop on Advances in Methods of Information and Communication Technology, AMICT’2009 - Petrozavodsk, Russian Federation
    Duration: 19 May 200920 May 2009

    Conference

    ConferenceAnnual International Workshop on Advances in Methods of Information and Communication Technology, AMICT’2009
    Abbreviated titleAMICT’2009
    CountryRussian Federation
    CityPetrozavodsk
    Period19/05/0920/05/09

    Keywords

    • Parallel computing
    • processor design
    • PRAM
    • shared memory

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  • Cite this

    Forsell, M., Leppänen, V., & Penttonen, M. (2009). Challenges of parallel processor design. In J. Kangasharju, & Y. A. Bogoyavlenskiy (Eds.), Proceedings of AMICT'2009: Annual International Workshop on Advances in Methods of Information and Communication Technology (pp. 75-87). Petrozavodskij gosudarstvenny`j universitet.