Clock-gating in FPGAs: A novel and comparative evaluation

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    26 Citations (Scopus)

    Abstract

    Clock-gating has been employed in low-power FPGA designs based on an emulated and compromised method. So far in literature the actual efficiency of savings in power consumption is not thoroughly studied for this method. In this paper we evaluated the clock-gating technique in FPGAs, based on a novel and comparative process. For a set of design cases, both the FPGA and ASIC clock-gating methods were implemented. Figures of power consumption were obtained using the corresponding FPGA/ASIC power estimation tools and devices. The results show that in FPGAs, the efficiency of savings in dynamic power consumption is about 50% to 80% of its ASIC counterparts. However, we also found that compared to ASICs, clock-gating for FPGAs in terms of the efficiency of savings in total average power consumption was only about 6% to 30% of its ASIC counterparts due to FPGA's large static power consumption.
    Original languageEnglish
    Title of host publication9th EUROMICRO Conference on Digital System Design (DSD'06)
    Pages584-588
    DOIs
    Publication statusPublished - 2006
    MoE publication typeA4 Article in a conference publication
    Event9th EUROMICRO Conference on Digital System Design, DSD06: Architectures, Methods and Tools - Dubrovnik, Croatia
    Duration: 30 Aug 20061 Sep 2006
    Conference number: 9

    Conference

    Conference9th EUROMICRO Conference on Digital System Design, DSD06
    Abbreviated titleDSD06
    CountryCroatia
    CityDubrovnik
    Period30/08/061/09/06

    Keywords

    • ASIC
    • integrated circuits
    • application specific integrated circuits
    • clocks
    • logic design
    • low-power electronics
    • clock-gating technique
    • field programmable gate array
    • low-power FPGA design
    • power consumption

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  • Cite this

    Zhang, Y., Roivainen, J., & Mämmelä, A. (2006). Clock-gating in FPGAs: A novel and comparative evaluation. In 9th EUROMICRO Conference on Digital System Design (DSD'06) (pp. 584-588) https://doi.org/10.1109/DSD.2006.32