Clock-gating in FPGAs: A novel and comparative evaluation

Yan Zhang; Jussi Roivainen; Aarne Mämmelä

doi:10.1109/DSD.2006.32

Clock-gating in FPGAs: A novel and comparative evaluation

Yan Zhang, Jussi Roivainen, Aarne Mämmelä

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

36 Citations (Scopus)

Abstract

Clock-gating has been employed in low-power FPGA designs based on an emulated and compromised method. So far in literature the actual efficiency of savings in power consumption is not thoroughly studied for this method. In this paper we evaluated the clock-gating technique in FPGAs, based on a novel and comparative process. For a set of design cases, both the FPGA and ASIC clock-gating methods were implemented. Figures of power consumption were obtained using the corresponding FPGA/ASIC power estimation tools and devices. The results show that in FPGAs, the efficiency of savings in dynamic power consumption is about 50% to 80% of its ASIC counterparts. However, we also found that compared to ASICs, clock-gating for FPGAs in terms of the efficiency of savings in total average power consumption was only about 6% to 30% of its ASIC counterparts due to FPGA's large static power consumption.

Original language	English
Title of host publication	9th EUROMICRO Conference on Digital System Design (DSD'06)
Pages	584-588
DOIs	https://doi.org/10.1109/DSD.2006.32
Publication status	Published - 2006
MoE publication type	A4 Article in a conference publication
Event	9th EUROMICRO Conference on Digital System Design, DSD06: Architectures, Methods and Tools - Dubrovnik, Croatia Duration: 30 Aug 2006 → 1 Sept 2006 Conference number: 9

Conference

Conference	9th EUROMICRO Conference on Digital System Design, DSD06
Abbreviated title	DSD06
Country/Territory	Croatia
City	Dubrovnik
Period	30/08/06 → 1/09/06

Keywords

ASIC
integrated circuits
application specific integrated circuits
clocks
logic design
low-power electronics
clock-gating technique
field programmable gate array
low-power FPGA design
power consumption

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10.1109/DSD.2006.32

Cite this

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title = "Clock-gating in FPGAs: A novel and comparative evaluation",

abstract = "Clock-gating has been employed in low-power FPGA designs based on an emulated and compromised method. So far in literature the actual efficiency of savings in power consumption is not thoroughly studied for this method. In this paper we evaluated the clock-gating technique in FPGAs, based on a novel and comparative process. For a set of design cases, both the FPGA and ASIC clock-gating methods were implemented. Figures of power consumption were obtained using the corresponding FPGA/ASIC power estimation tools and devices. The results show that in FPGAs, the efficiency of savings in dynamic power consumption is about 50% to 80% of its ASIC counterparts. However, we also found that compared to ASICs, clock-gating for FPGAs in terms of the efficiency of savings in total average power consumption was only about 6% to 30% of its ASIC counterparts due to FPGA's large static power consumption.",

keywords = "ASIC, integrated circuits, application specific integrated circuits, clocks, logic design, low-power electronics, clock-gating technique, field programmable gate array, low-power FPGA design, power consumption",

author = "Yan Zhang and Jussi Roivainen and Aarne M{\"a}mmel{\"a}",

year = "2006",

doi = "10.1109/DSD.2006.32",

language = "English",

isbn = "0-7695-2609-8",

pages = "584--588",

booktitle = "9th EUROMICRO Conference on Digital System Design (DSD'06)",

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AU - Zhang, Yan

AU - Roivainen, Jussi

AU - Mämmelä, Aarne

N1 - Conference code: 9

PY - 2006

Y1 - 2006

N2 - Clock-gating has been employed in low-power FPGA designs based on an emulated and compromised method. So far in literature the actual efficiency of savings in power consumption is not thoroughly studied for this method. In this paper we evaluated the clock-gating technique in FPGAs, based on a novel and comparative process. For a set of design cases, both the FPGA and ASIC clock-gating methods were implemented. Figures of power consumption were obtained using the corresponding FPGA/ASIC power estimation tools and devices. The results show that in FPGAs, the efficiency of savings in dynamic power consumption is about 50% to 80% of its ASIC counterparts. However, we also found that compared to ASICs, clock-gating for FPGAs in terms of the efficiency of savings in total average power consumption was only about 6% to 30% of its ASIC counterparts due to FPGA's large static power consumption.

AB - Clock-gating has been employed in low-power FPGA designs based on an emulated and compromised method. So far in literature the actual efficiency of savings in power consumption is not thoroughly studied for this method. In this paper we evaluated the clock-gating technique in FPGAs, based on a novel and comparative process. For a set of design cases, both the FPGA and ASIC clock-gating methods were implemented. Figures of power consumption were obtained using the corresponding FPGA/ASIC power estimation tools and devices. The results show that in FPGAs, the efficiency of savings in dynamic power consumption is about 50% to 80% of its ASIC counterparts. However, we also found that compared to ASICs, clock-gating for FPGAs in terms of the efficiency of savings in total average power consumption was only about 6% to 30% of its ASIC counterparts due to FPGA's large static power consumption.

KW - ASIC

KW - integrated circuits

KW - application specific integrated circuits

KW - clocks

KW - logic design

KW - low-power electronics

KW - clock-gating technique

KW - field programmable gate array

KW - low-power FPGA design

KW - power consumption

U2 - 10.1109/DSD.2006.32

DO - 10.1109/DSD.2006.32

M3 - Conference article in proceedings

SN - 0-7695-2609-8

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EP - 588

BT - 9th EUROMICRO Conference on Digital System Design (DSD'06)

Y2 - 30 August 2006 through 1 September 2006

ER -

Clock-gating in FPGAs: A novel and comparative evaluation

Abstract

Conference

Keywords

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