Column-Wise IR-Drop Calibration for RRAM-Based CIM: Validation Using a Hierarchical Verilog-A Modeling Framework

Omar Numan; Jelin Leslin; Gaurav Singh; Kazybek Adam; Martin Andraud; Kari Halonen

doi:10.1109/EDTM65772.2026.11496715

Column-Wise IR-Drop Calibration for RRAM-Based CIM: Validation Using a Hierarchical Verilog-A Modeling Framework

Omar Numan
, Jelin Leslin
, Gaurav Singh
, Kazybek Adam
, Martin Andraud
, Kari Halonen

Not published at VTT

Aalto University
Catholic University of Louvain

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

Abstract

Column-wise IR-drop and readout nonidealities significantly degrade the inference accuracy of resistive compute-in-memory (CIM) accelerators. This paper proposes a lightweight calibration circuit integrated in the current-mode readout path to restore column linearity and suppress IR-drop-induced errors. To evaluate and validate the design before fabrication, a hierarchical Verilog-A modeling framework is developed to enable SPICE-compatible co-simulation of mixed-signal CIM arrays and convolutional neural networks (CNNs). The proposed calibration—based on an R–2R multiplying DAC and digital error correction logic—is implemented and verified by replacing its behavioral submodules with transistor-level netlists. Using a modified LeNet trained on MNIST, the framework achieves over 95% accuracy recovery under 20% column-conductance variation, demonstrating strong circuit–system correlation.

Original language	English
Title of host publication	2026 10th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
Publisher	IEEE Institute of Electrical and Electronic Engineers
Number of pages	3
ISBN (Electronic)	979-8-3315-8598-3
DOIs	https://doi.org/10.1109/EDTM65772.2026.11496715
Publication status	Published - 4 Mar 2026
MoE publication type	A4 Article in a conference publication
Event	2026 10th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) - Penang, Malaysia Duration: 1 Mar 2026 → 4 Mar 2026

Conference

Conference	2026 10th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
Period	1/03/26 → 4/03/26

Keywords

Circuits
Circuits and systems
Integrated circuits
Circuit simulation
Circuit synthesis
Neuromorphics
Media Access Control
Protocols
HTTP
5G mobile communication

Access to Document

10.1109/EDTM65772.2026.11496715

Cite this

Numan, O., Leslin, J., Singh, G., Adam, K., Andraud, M., & Halonen, K. (2026). Column-Wise IR-Drop Calibration for RRAM-Based CIM: Validation Using a Hierarchical Verilog-A Modeling Framework. In 2026 10th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.1109/EDTM65772.2026.11496715

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title = "Column-Wise IR-Drop Calibration for RRAM-Based CIM: Validation Using a Hierarchical Verilog-A Modeling Framework",

abstract = "Column-wise IR-drop and readout nonidealities significantly degrade the inference accuracy of resistive compute-in-memory (CIM) accelerators. This paper proposes a lightweight calibration circuit integrated in the current-mode readout path to restore column linearity and suppress IR-drop-induced errors. To evaluate and validate the design before fabrication, a hierarchical Verilog-A modeling framework is developed to enable SPICE-compatible co-simulation of mixed-signal CIM arrays and convolutional neural networks (CNNs). The proposed calibration—based on an R–2R multiplying DAC and digital error correction logic—is implemented and verified by replacing its behavioral submodules with transistor-level netlists. Using a modified LeNet trained on MNIST, the framework achieves over 95\% accuracy recovery under 20\% column-conductance variation, demonstrating strong circuit–system correlation.",

keywords = "Circuits, Circuits and systems, Integrated circuits, Circuit simulation, Circuit synthesis, Neuromorphics, Media Access Control, Protocols, HTTP, 5G mobile communication",

author = "Omar Numan and Jelin Leslin and Gaurav Singh and Kazybek Adam and Martin Andraud and Kari Halonen",

year = "2026",

month = mar,

day = "4",

doi = "10.1109/EDTM65772.2026.11496715",

language = "English",

booktitle = "2026 10th IEEE Electron Devices Technology \& Manufacturing Conference (EDTM)",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

note = "2026 10th IEEE Electron Devices Technology \& Manufacturing Conference (EDTM) ; Conference date: 01-03-2026 Through 04-03-2026",

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Numan, O, Leslin, J, Singh, G, Adam, K, Andraud, M & Halonen, K 2026, Column-Wise IR-Drop Calibration for RRAM-Based CIM: Validation Using a Hierarchical Verilog-A Modeling Framework. in 2026 10th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE Institute of Electrical and Electronic Engineers, 2026 10th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1/03/26. https://doi.org/10.1109/EDTM65772.2026.11496715

Column-Wise IR-Drop Calibration for RRAM-Based CIM: Validation Using a Hierarchical Verilog-A Modeling Framework. / Numan, Omar; Leslin, Jelin; Singh, Gaurav et al.
2026 10th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE Institute of Electrical and Electronic Engineers, 2026.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

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AU - Leslin, Jelin

AU - Singh, Gaurav

AU - Adam, Kazybek

AU - Andraud, Martin

AU - Halonen, Kari

PY - 2026/3/4

Y1 - 2026/3/4

N2 - Column-wise IR-drop and readout nonidealities significantly degrade the inference accuracy of resistive compute-in-memory (CIM) accelerators. This paper proposes a lightweight calibration circuit integrated in the current-mode readout path to restore column linearity and suppress IR-drop-induced errors. To evaluate and validate the design before fabrication, a hierarchical Verilog-A modeling framework is developed to enable SPICE-compatible co-simulation of mixed-signal CIM arrays and convolutional neural networks (CNNs). The proposed calibration—based on an R–2R multiplying DAC and digital error correction logic—is implemented and verified by replacing its behavioral submodules with transistor-level netlists. Using a modified LeNet trained on MNIST, the framework achieves over 95% accuracy recovery under 20% column-conductance variation, demonstrating strong circuit–system correlation.

AB - Column-wise IR-drop and readout nonidealities significantly degrade the inference accuracy of resistive compute-in-memory (CIM) accelerators. This paper proposes a lightweight calibration circuit integrated in the current-mode readout path to restore column linearity and suppress IR-drop-induced errors. To evaluate and validate the design before fabrication, a hierarchical Verilog-A modeling framework is developed to enable SPICE-compatible co-simulation of mixed-signal CIM arrays and convolutional neural networks (CNNs). The proposed calibration—based on an R–2R multiplying DAC and digital error correction logic—is implemented and verified by replacing its behavioral submodules with transistor-level netlists. Using a modified LeNet trained on MNIST, the framework achieves over 95% accuracy recovery under 20% column-conductance variation, demonstrating strong circuit–system correlation.

KW - Circuits

KW - Circuits and systems

KW - Integrated circuits

KW - Circuit simulation

KW - Circuit synthesis

KW - Neuromorphics

KW - Media Access Control

KW - Protocols

KW - HTTP

KW - 5G mobile communication

U2 - 10.1109/EDTM65772.2026.11496715

DO - 10.1109/EDTM65772.2026.11496715

M3 - Conference article in proceedings

BT - 2026 10th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - 2026 10th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)

Y2 - 1 March 2026 through 4 March 2026

ER -

Column-Wise IR-Drop Calibration for RRAM-Based CIM: Validation Using a Hierarchical Verilog-A Modeling Framework

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Conference

Keywords

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