Comparative performance of MoS₂ transistors: Statistical study and one-transistor-one-resistive memory integration

To advance the technology readiness level of the field effect transistors (FETs) based on multilayer two-dimensional (2D) molybdenum disulfide (MoS₂), we conducted a large-scale statistical study with approximately 400 FETs fabricated on a silicon wafer. Our study examines the influence of two complementary metal oxide semiconductor (CMOS)-compatible gate metal materials with Nb being used for the first time in MoS₂ FET, on the device performance and demonstrates the integration potential with resistive memory element. Transistors with varied channel dimensions were fabricated using each gate metal in an identical back gate, top contact structure and layout. Low-temperature processes (below 300 °C) were employed to ensure applicability to flexible electronics. Our MoS₂ transistors achieved ON current (Ion) of up to ∼100 μA at a source-drain voltage (VDS) of 2.5 V for the transistor with a 160 μm-wide channel on/off current ratio of 108, and a threshold voltage of 1.8 V when measured in an ambient environment. While Ion, contact resistance (RC), and subthreshold swing (SS) were improved with titanium nitride (TiN) gate metal, gate hysteresis was reduced in Nb-gated transistors. The transistors with TiN gate metal showed on resistance (Ron) of 5 Ω m and SS as low as 100 mV/dec. For demonstration, following FET fabrication, we applied a dielectric passivation layer to facilitate the post processing, then co-integrated a memory element with transistor to implement a one transistor-one resistive memory (1T1R) structure achieving over 100 direct-current (DC) switching cycles, thereby validating the feasibility of post-processing of MoS₂-transistor at low temperatures.