Abstract
With the modern chip design facing the so called frequency, power and other walls, multi-core systems have become dominant. Due to the relatively large operating cost of fine-grained parallelism, the systems are often task-oriented. With the recent appearance of more synchronous platforms for parallel computing, we propose a language supported task system optimization for strictly synchronous multi-core architectures equipped with hardware accelerated multi-prefix operations and other finite resources (with respect to concurrent access). The purpose of this system is to dynamically manage the error prone allocation of such resources, yet provide reasonable performance speedups without placing the burden of resource management to the programmer. Our system compiles several specialized versions of accelerated functions that are dynamically picked by the runtime task system based on the tasks' requirements and the resource availability.
Original language | English |
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Title of host publication | CompSysTech '16 Proceedings of the 17th International Conference on Computer Systems and Technologies 2016 |
Publisher | Association for Computing Machinery ACM |
Pages | 49-56 |
ISBN (Print) | 978-1-4503-4182-0 |
DOIs | |
Publication status | Published - 2016 |
MoE publication type | A4 Article in a conference publication |
Event | 17th International Conference on Computer Systems and Technologies, CompSysTech 2016 - Palermo, Italy Duration: 23 Jun 2016 → 24 Jun 2016 Conference number: 17 |
Conference
Conference | 17th International Conference on Computer Systems and Technologies, CompSysTech 2016 |
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Abbreviated title | CompSysTech 2016 |
Country/Territory | Italy |
City | Palermo |
Period | 23/06/16 → 24/06/16 |
Keywords
- active memory
- flow analysis
- parallel programming
- task parallel