Configurable DSP engine for internet age

Antti Pelkonen; Juha-Pekka Soininen; Tapio Rautio

Configurable DSP engine for internet age

Antti Pelkonen, Juha-Pekka Soininen, Tapio Rautio

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

Abstract

Description of configurable digital signal processing architecture for multimedia and internet communications comprising of virtual components, such as processor cores, memories and buses. The architecture is analysed using MPEG-2 decoder and HiperLAN/2 modem functionality.

Original language	English
Title of host publication	Proceedings of the 2001 19th Norchip Conference
Publisher	Technoconsult
Pages	47-52
ISBN (Print)	87-982637-3-0
Publication status	Published - 2001
MoE publication type	A4 Article in a conference publication
Event	19th IEEE Norchip Conference, NORCHIP 2001 - Kista, Sweden Duration: 12 Nov 2001 → 13 Nov 2001

Conference

Conference	19th IEEE Norchip Conference, NORCHIP 2001
Country/Territory	Sweden
City	Kista
Period	12/11/01 → 13/11/01

Cite this

@inproceedings{e9745f26cfd243dab2746c21e59314c1,

title = "Configurable DSP engine for internet age",

abstract = "Description of configurable digital signal processing architecture for multimedia and internet communications comprising of virtual components, such as processor cores, memories and buses. The architecture is analysed using MPEG-2 decoder and HiperLAN/2 modem functionality.",

author = "Antti Pelkonen and Juha-Pekka Soininen and Tapio Rautio",

year = "2001",

language = "English",

isbn = "87-982637-3-0",

pages = "47--52",

booktitle = "Proceedings of the 2001 19th Norchip Conference",

publisher = "Technoconsult",

address = "Denmark",

note = "19th IEEE Norchip Conference, NORCHIP 2001 ; Conference date: 12-11-2001 Through 13-11-2001",

}

TY - GEN

T1 - Configurable DSP engine for internet age

AU - Pelkonen, Antti

AU - Soininen, Juha-Pekka

AU - Rautio, Tapio

PY - 2001

Y1 - 2001

N2 - Description of configurable digital signal processing architecture for multimedia and internet communications comprising of virtual components, such as processor cores, memories and buses. The architecture is analysed using MPEG-2 decoder and HiperLAN/2 modem functionality.

AB - Description of configurable digital signal processing architecture for multimedia and internet communications comprising of virtual components, such as processor cores, memories and buses. The architecture is analysed using MPEG-2 decoder and HiperLAN/2 modem functionality.

M3 - Conference article in proceedings

SN - 87-982637-3-0

SP - 47

EP - 52

BT - Proceedings of the 2001 19th Norchip Conference

PB - Technoconsult

T2 - 19th IEEE Norchip Conference, NORCHIP 2001

Y2 - 12 November 2001 through 13 November 2001

ER -

Configurable DSP engine for internet age

Abstract

Conference

Fingerprint

Cite this