Configurable DSP engine for internet age

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

Abstract

Description of configurable digital signal processing architecture for multimedia and internet communications comprising of virtual components, such as processor cores, memories and buses. The architecture is analysed using MPEG-2 decoder and HiperLAN/2 modem functionality.
Original languageEnglish
Title of host publicationProceedings of the 2001 19th Norchip Conference
PublisherTechnoconsult
Pages47-52
ISBN (Print)87-982637-3-0
Publication statusPublished - 2001
MoE publication typeA4 Article in a conference publication
Event19th IEEE Norchip Conference, NORCHIP 2001 - Kista, Sweden
Duration: 12 Nov 200113 Nov 2001

Conference

Conference19th IEEE Norchip Conference, NORCHIP 2001
CountrySweden
CityKista
Period12/11/0113/11/01

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