Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

7 Citations (Scopus)

Abstract

Emulated shared memory (ESM) multiprocessor systems on chip (MP-SOC) and network on chip (NOC) regions are efficient general purpose computing engines for future computers and embedded systems running applications unknown at the design phase. While they provide programmer a synchronous, unified, and constant time accessible shared memory, the existing ESM architectures have been shown to be inefficient with workloads having low parallelism. In this paper we outline a configurable emulated shared memory (CESM) architecture that retains the advantages of the ESM architectures for parallel enough code but is also able to execute applications with low parallelism efficiently. This happens by allowing multiple threads to join as a single nonuniform memory access (NUMA) bunch and organizing memory system to support NUMA-like behavior for thread-local data if parallelism is limited. Performance simulations as well as silicon area and power consumption estimations of CESM MP-SOC/ NOC regions are provided. (23 refs.)
Original languageEnglish
Title of host publication3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'09). San Diego, CA, USA, 10 - 13 May 2009.
Place of PublicationPiscataway
PublisherIEEE Institute of Electrical and Electronic Engineers
Pages163-172
ISBN (Print)978-1-4244-4142-6
DOIs
Publication statusPublished - 2009
MoE publication typeA4 Article in a conference publication
Event3rd ACM/IEEE International Symposium on Networks-on-Chip, NOCS'09 - San Diego, United States
Duration: 10 May 200913 May 2009

Conference

Conference3rd ACM/IEEE International Symposium on Networks-on-Chip, NOCS'09
Abbreviated titleNOCS'09
CountryUnited States
CitySan Diego
Period10/05/0913/05/09

Fingerprint

Memory architecture
Data storage equipment
Computer systems
Embedded systems
Network-on-chip
Electric power utilization
Engines
Silicon

Keywords

  • Parallel computing
  • MP-SOC
  • NOC
  • emulated shared memory
  • PRAM
  • NUMA

Cite this

Forsell, M. (2009). Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions. In 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'09). San Diego, CA, USA, 10 - 13 May 2009. (pp. 163-172). Piscataway: IEEE Institute of Electrical and Electronic Engineers . https://doi.org/10.1109/NOCS.2009.5071464
Forsell, Martti. / Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions. 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'09). San Diego, CA, USA, 10 - 13 May 2009.. Piscataway : IEEE Institute of Electrical and Electronic Engineers , 2009. pp. 163-172
@inproceedings{6e33129ad265408bb79451359f3bc810,
title = "Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions",
abstract = "Emulated shared memory (ESM) multiprocessor systems on chip (MP-SOC) and network on chip (NOC) regions are efficient general purpose computing engines for future computers and embedded systems running applications unknown at the design phase. While they provide programmer a synchronous, unified, and constant time accessible shared memory, the existing ESM architectures have been shown to be inefficient with workloads having low parallelism. In this paper we outline a configurable emulated shared memory (CESM) architecture that retains the advantages of the ESM architectures for parallel enough code but is also able to execute applications with low parallelism efficiently. This happens by allowing multiple threads to join as a single nonuniform memory access (NUMA) bunch and organizing memory system to support NUMA-like behavior for thread-local data if parallelism is limited. Performance simulations as well as silicon area and power consumption estimations of CESM MP-SOC/ NOC regions are provided. (23 refs.)",
keywords = "Parallel computing, MP-SOC, NOC, emulated shared memory, PRAM, NUMA",
author = "Martti Forsell",
year = "2009",
doi = "10.1109/NOCS.2009.5071464",
language = "English",
isbn = "978-1-4244-4142-6",
pages = "163--172",
booktitle = "3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'09). San Diego, CA, USA, 10 - 13 May 2009.",
publisher = "IEEE Institute of Electrical and Electronic Engineers",
address = "United States",

}

Forsell, M 2009, Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions. in 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'09). San Diego, CA, USA, 10 - 13 May 2009.. IEEE Institute of Electrical and Electronic Engineers , Piscataway, pp. 163-172, 3rd ACM/IEEE International Symposium on Networks-on-Chip, NOCS'09, San Diego, United States, 10/05/09. https://doi.org/10.1109/NOCS.2009.5071464

Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions. / Forsell, Martti.

3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'09). San Diego, CA, USA, 10 - 13 May 2009.. Piscataway : IEEE Institute of Electrical and Electronic Engineers , 2009. p. 163-172.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

TY - GEN

T1 - Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions

AU - Forsell, Martti

PY - 2009

Y1 - 2009

N2 - Emulated shared memory (ESM) multiprocessor systems on chip (MP-SOC) and network on chip (NOC) regions are efficient general purpose computing engines for future computers and embedded systems running applications unknown at the design phase. While they provide programmer a synchronous, unified, and constant time accessible shared memory, the existing ESM architectures have been shown to be inefficient with workloads having low parallelism. In this paper we outline a configurable emulated shared memory (CESM) architecture that retains the advantages of the ESM architectures for parallel enough code but is also able to execute applications with low parallelism efficiently. This happens by allowing multiple threads to join as a single nonuniform memory access (NUMA) bunch and organizing memory system to support NUMA-like behavior for thread-local data if parallelism is limited. Performance simulations as well as silicon area and power consumption estimations of CESM MP-SOC/ NOC regions are provided. (23 refs.)

AB - Emulated shared memory (ESM) multiprocessor systems on chip (MP-SOC) and network on chip (NOC) regions are efficient general purpose computing engines for future computers and embedded systems running applications unknown at the design phase. While they provide programmer a synchronous, unified, and constant time accessible shared memory, the existing ESM architectures have been shown to be inefficient with workloads having low parallelism. In this paper we outline a configurable emulated shared memory (CESM) architecture that retains the advantages of the ESM architectures for parallel enough code but is also able to execute applications with low parallelism efficiently. This happens by allowing multiple threads to join as a single nonuniform memory access (NUMA) bunch and organizing memory system to support NUMA-like behavior for thread-local data if parallelism is limited. Performance simulations as well as silicon area and power consumption estimations of CESM MP-SOC/ NOC regions are provided. (23 refs.)

KW - Parallel computing

KW - MP-SOC

KW - NOC

KW - emulated shared memory

KW - PRAM

KW - NUMA

U2 - 10.1109/NOCS.2009.5071464

DO - 10.1109/NOCS.2009.5071464

M3 - Conference article in proceedings

SN - 978-1-4244-4142-6

SP - 163

EP - 172

BT - 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'09). San Diego, CA, USA, 10 - 13 May 2009.

PB - IEEE Institute of Electrical and Electronic Engineers

CY - Piscataway

ER -

Forsell M. Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions. In 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'09). San Diego, CA, USA, 10 - 13 May 2009.. Piscataway: IEEE Institute of Electrical and Electronic Engineers . 2009. p. 163-172 https://doi.org/10.1109/NOCS.2009.5071464