Configurable memory organisation for communication applications

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    2 Citations (Scopus)

    Abstract

    A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done by controlling the DSP processor's access to memory buses with an external processor and switches. The configurable memory organisation allows the scaling of system capacity to the needs of the applications and makes the use of the capacity more effective. The architecture was modelled and evaluated using a systemC simulator and workload models. The clock frequency can be reduced by up to 25% if a configurable memory system is used instead of a bus-based shared memory. The memory latency with configurable memory organisation was less than 50% of the latency of the shared memory solution.
    Original languageEnglish
    Title of host publicationProceedings Euromicro Symposium on Digital System Design
    Subtitle of host publicationArchitecture, Methods and Tools
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Pages86-93
    ISBN (Print)0-7695-1790-0
    DOIs
    Publication statusPublished - 2002
    MoE publication typeA4 Article in a conference publication
    EventEuromicro Symposium on Digital System Design, DSD 2002 - Dortmund, Germany
    Duration: 4 Sep 20026 Sep 2002

    Conference

    ConferenceEuromicro Symposium on Digital System Design, DSD 2002
    CountryGermany
    CityDortmund
    Period4/09/026/09/02

    Keywords

    • Memory organisation
    • configurability
    • System-on-chip
    • workload simulation

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