Configurable memory organisation for communication applications

Juha-Pekka Soininen; Antti Pelkonen; Jussi Roivainen

doi:10.1109/DSD.2002.1115355

Configurable memory organisation for communication applications

Juha-Pekka Soininen, Antti Pelkonen, Jussi Roivainen

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

3 Citations (Scopus)

Abstract

A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done by controlling the DSP processor's access to memory buses with an external processor and switches. The configurable memory organisation allows the scaling of system capacity to the needs of the applications and makes the use of the capacity more effective. The architecture was modelled and evaluated using a systemC simulator and workload models. The clock frequency can be reduced by up to 25% if a configurable memory system is used instead of a bus-based shared memory. The memory latency with configurable memory organisation was less than 50% of the latency of the shared memory solution.

Original language	English
Title of host publication	Proceedings Euromicro Symposium on Digital System Design
Subtitle of host publication	Architecture, Methods and Tools
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	86-93
ISBN (Print)	0-7695-1790-0
DOIs	https://doi.org/10.1109/DSD.2002.1115355
Publication status	Published - 2002
MoE publication type	A4 Article in a conference publication
Event	Euromicro Symposium on Digital System Design, DSD 2002 - Dortmund, Germany Duration: 4 Sept 2002 → 6 Sept 2002

Conference

Conference	Euromicro Symposium on Digital System Design, DSD 2002
Country/Territory	Germany
City	Dortmund
Period	4/09/02 → 6/09/02

Keywords

Memory organisation
configurability
System-on-chip
workload simulation

Access to Document

10.1109/DSD.2002.1115355

Cite this

@inproceedings{2bc949b0e22f42f48432c41b1edffd6d,

title = "Configurable memory organisation for communication applications",

abstract = "A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done by controlling the DSP processor's access to memory buses with an external processor and switches. The configurable memory organisation allows the scaling of system capacity to the needs of the applications and makes the use of the capacity more effective. The architecture was modelled and evaluated using a systemC simulator and workload models. The clock frequency can be reduced by up to 25% if a configurable memory system is used instead of a bus-based shared memory. The memory latency with configurable memory organisation was less than 50% of the latency of the shared memory solution.",

keywords = "Memory organisation, configurability, System-on-chip, workload simulation",

author = "Juha-Pekka Soininen and Antti Pelkonen and Jussi Roivainen",

year = "2002",

doi = "10.1109/DSD.2002.1115355",

language = "English",

isbn = "0-7695-1790-0",

pages = "86--93",

booktitle = "Proceedings Euromicro Symposium on Digital System Design",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

note = "Euromicro Symposium on Digital System Design, DSD 2002 ; Conference date: 04-09-2002 Through 06-09-2002",

}

Soininen, J-P, Pelkonen, A & Roivainen, J 2002, Configurable memory organisation for communication applications. in Proceedings Euromicro Symposium on Digital System Design: Architecture, Methods and Tools. IEEE Institute of Electrical and Electronic Engineers, pp. 86-93, Euromicro Symposium on Digital System Design, DSD 2002, Dortmund, Germany, 4/09/02. https://doi.org/10.1109/DSD.2002.1115355

Configurable memory organisation for communication applications. / Soininen, Juha-Pekka; Pelkonen, Antti; Roivainen, Jussi.
Proceedings Euromicro Symposium on Digital System Design: Architecture, Methods and Tools. IEEE Institute of Electrical and Electronic Engineers, 2002. p. 86-93.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - Configurable memory organisation for communication applications

AU - Soininen, Juha-Pekka

AU - Pelkonen, Antti

AU - Roivainen, Jussi

PY - 2002

Y1 - 2002

N2 - A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done by controlling the DSP processor's access to memory buses with an external processor and switches. The configurable memory organisation allows the scaling of system capacity to the needs of the applications and makes the use of the capacity more effective. The architecture was modelled and evaluated using a systemC simulator and workload models. The clock frequency can be reduced by up to 25% if a configurable memory system is used instead of a bus-based shared memory. The memory latency with configurable memory organisation was less than 50% of the latency of the shared memory solution.

AB - A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done by controlling the DSP processor's access to memory buses with an external processor and switches. The configurable memory organisation allows the scaling of system capacity to the needs of the applications and makes the use of the capacity more effective. The architecture was modelled and evaluated using a systemC simulator and workload models. The clock frequency can be reduced by up to 25% if a configurable memory system is used instead of a bus-based shared memory. The memory latency with configurable memory organisation was less than 50% of the latency of the shared memory solution.

KW - Memory organisation

KW - configurability

KW - System-on-chip

KW - workload simulation

U2 - 10.1109/DSD.2002.1115355

DO - 10.1109/DSD.2002.1115355

M3 - Conference article in proceedings

SN - 0-7695-1790-0

SP - 86

EP - 93

BT - Proceedings Euromicro Symposium on Digital System Design

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - Euromicro Symposium on Digital System Design, DSD 2002

Y2 - 4 September 2002 through 6 September 2002

ER -

Configurable memory organisation for communication applications

Abstract

Conference

Keywords

Access to Document

Fingerprint

Cite this