Cost of sparse mesh layouts supporting throughput computing

Martti Forsell, V. Leppänen, M. Penttonen

    Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific

    3 Citations (Scopus)

    Abstract

    The purpose of this paper is to estimate the cost of utilizing underpopulated, or sparse, networks on chip (NOC) for chip multiprocessors (CMP). In underpopulated NOCs, only a portion of nodes are sources and sinks whereas the rest are simple intermediate nodes increasing communication bandwidth. Compared to dense NOCs, where all nodes can be sources and sinks of communication, the underpopulated NOCs can be scaled so that any degree of communication frequency of nodes can be supported. The drawback of underpopulated NOCs is larger network area and bigger logical diameter. GPGPU-style stream-based or high-throughput CMPs can be used to hide the effect of longer latencies. In this paper, we present layouts for mesh-based underpopulated networks, calculate their wirelength distributions and the overall area. Moreover, we present energy consumption calculations for such networks, and show that while the network part of a CMP system based on underpopulated NOCs can play a major role when considering the chip area and energy consumption, it can be pushed down by increasing the number of dimensions and using meshes instead of tori. We also compare various multidimensional sparse meshlayouts and conclude the 3-dimensional and 4-dimensional sparse meshes to be the most attractive ones for throughput computing
    Original languageEnglish
    Title of host publicationProceedings
    Subtitle of host publication14th Euromicro Conference on Digital System Design, DSD 2011
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Pages316-323
    ISBN (Print)978-1-4577-1048-3
    DOIs
    Publication statusPublished - 2011
    MoE publication typeB3 Non-refereed article in conference proceedings
    Event14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011 - Oulu, Finland
    Duration: 31 Aug 2011 → 2 Sep 2011

    Conference

    Conference14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011
    Abbreviated titleDSD 2011
    CountryFinland
    CityOulu
    Period31/08/11 → 2/09/11

    Fingerprint

    Throughput
    Communication
    Energy utilization
    Costs
    Bandwidth
    Network-on-chip

    Keywords

    • Comparison
    • layouts
    • network on chip
    • sparse networks
    • throughput computing

    Cite this

    Forsell, M., Leppänen, V., & Penttonen, M. (2011). Cost of sparse mesh layouts supporting throughput computing. In Proceedings: 14th Euromicro Conference on Digital System Design, DSD 2011 (pp. 316-323). IEEE Institute of Electrical and Electronic Engineers . https://doi.org/10.1109/DSD.2011.46
    Forsell, Martti ; Leppänen, V. ; Penttonen, M. / Cost of sparse mesh layouts supporting throughput computing. Proceedings: 14th Euromicro Conference on Digital System Design, DSD 2011. IEEE Institute of Electrical and Electronic Engineers , 2011. pp. 316-323
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    Forsell, M, Leppänen, V & Penttonen, M 2011, Cost of sparse mesh layouts supporting throughput computing. in Proceedings: 14th Euromicro Conference on Digital System Design, DSD 2011. IEEE Institute of Electrical and Electronic Engineers , pp. 316-323, 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011, Oulu, Finland, 31/08/11. https://doi.org/10.1109/DSD.2011.46

    Cost of sparse mesh layouts supporting throughput computing. / Forsell, Martti; Leppänen, V.; Penttonen, M.

    Proceedings: 14th Euromicro Conference on Digital System Design, DSD 2011. IEEE Institute of Electrical and Electronic Engineers , 2011. p. 316-323.

    Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific

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    N2 - The purpose of this paper is to estimate the cost of utilizing underpopulated, or sparse, networks on chip (NOC) for chip multiprocessors (CMP). In underpopulated NOCs, only a portion of nodes are sources and sinks whereas the rest are simple intermediate nodes increasing communication bandwidth. Compared to dense NOCs, where all nodes can be sources and sinks of communication, the underpopulated NOCs can be scaled so that any degree of communication frequency of nodes can be supported. The drawback of underpopulated NOCs is larger network area and bigger logical diameter. GPGPU-style stream-based or high-throughput CMPs can be used to hide the effect of longer latencies. In this paper, we present layouts for mesh-based underpopulated networks, calculate their wirelength distributions and the overall area. Moreover, we present energy consumption calculations for such networks, and show that while the network part of a CMP system based on underpopulated NOCs can play a major role when considering the chip area and energy consumption, it can be pushed down by increasing the number of dimensions and using meshes instead of tori. We also compare various multidimensional sparse meshlayouts and conclude the 3-dimensional and 4-dimensional sparse meshes to be the most attractive ones for throughput computing

    AB - The purpose of this paper is to estimate the cost of utilizing underpopulated, or sparse, networks on chip (NOC) for chip multiprocessors (CMP). In underpopulated NOCs, only a portion of nodes are sources and sinks whereas the rest are simple intermediate nodes increasing communication bandwidth. Compared to dense NOCs, where all nodes can be sources and sinks of communication, the underpopulated NOCs can be scaled so that any degree of communication frequency of nodes can be supported. The drawback of underpopulated NOCs is larger network area and bigger logical diameter. GPGPU-style stream-based or high-throughput CMPs can be used to hide the effect of longer latencies. In this paper, we present layouts for mesh-based underpopulated networks, calculate their wirelength distributions and the overall area. Moreover, we present energy consumption calculations for such networks, and show that while the network part of a CMP system based on underpopulated NOCs can play a major role when considering the chip area and energy consumption, it can be pushed down by increasing the number of dimensions and using meshes instead of tori. We also compare various multidimensional sparse meshlayouts and conclude the 3-dimensional and 4-dimensional sparse meshes to be the most attractive ones for throughput computing

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    Forsell M, Leppänen V, Penttonen M. Cost of sparse mesh layouts supporting throughput computing. In Proceedings: 14th Euromicro Conference on Digital System Design, DSD 2011. IEEE Institute of Electrical and Electronic Engineers . 2011. p. 316-323 https://doi.org/10.1109/DSD.2011.46

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