Cost of sparse mesh layouts supporting throughput computing

Martti Forsell; V. Leppänen; M. Penttonen

doi:10.1109/DSD.2011.46

Cost of sparse mesh layouts supporting throughput computing

Martti Forsell, V. Leppänen, M. Penttonen

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific

3 Citations (Scopus)

Abstract

The purpose of this paper is to estimate the cost of utilizing underpopulated, or sparse, networks on chip (NOC) for chip multiprocessors (CMP). In underpopulated NOCs, only a portion of nodes are sources and sinks whereas the rest are simple intermediate nodes increasing communication bandwidth. Compared to dense NOCs, where all nodes can be sources and sinks of communication, the underpopulated NOCs can be scaled so that any degree of communication frequency of nodes can be supported. The drawback of underpopulated NOCs is larger network area and bigger logical diameter. GPGPU-style stream-based or high-throughput CMPs can be used to hide the effect of longer latencies. In this paper, we present layouts for mesh-based underpopulated networks, calculate their wirelength distributions and the overall area. Moreover, we present energy consumption calculations for such networks, and show that while the network part of a CMP system based on underpopulated NOCs can play a major role when considering the chip area and energy consumption, it can be pushed down by increasing the number of dimensions and using meshes instead of tori. We also compare various multidimensional sparse meshlayouts and conclude the 3-dimensional and 4-dimensional sparse meshes to be the most attractive ones for throughput computing

Original language	English
Title of host publication	Proceedings
Subtitle of host publication	14th Euromicro Conference on Digital System Design, DSD 2011
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	316-323
ISBN (Print)	978-1-4577-1048-3
DOIs	https://doi.org/10.1109/DSD.2011.46
Publication status	Published - 2011
MoE publication type	B3 Non-refereed article in conference proceedings
Event	14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011 - Oulu, Finland Duration: 31 Aug 2011 → 2 Sep 2011

Conference

Conference	14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011
Abbreviated title	DSD 2011
Country	Finland
City	Oulu
Period	31/08/11 → 2/09/11

Fingerprint

Keywords

Comparison
layouts
network on chip
sparse networks
throughput computing

Cite this

Forsell, M., Leppänen, V., & Penttonen, M. (2011). Cost of sparse mesh layouts supporting throughput computing. In Proceedings: 14th Euromicro Conference on Digital System Design, DSD 2011 (pp. 316-323). IEEE Institute of Electrical and Electronic Engineers . https://doi.org/10.1109/DSD.2011.46

@inproceedings{481d73ba5e51455193dede8df8d4c052,

title = "Cost of sparse mesh layouts supporting throughput computing",

abstract = "The purpose of this paper is to estimate the cost of utilizing underpopulated, or sparse, networks on chip (NOC) for chip multiprocessors (CMP). In underpopulated NOCs, only a portion of nodes are sources and sinks whereas the rest are simple intermediate nodes increasing communication bandwidth. Compared to dense NOCs, where all nodes can be sources and sinks of communication, the underpopulated NOCs can be scaled so that any degree of communication frequency of nodes can be supported. The drawback of underpopulated NOCs is larger network area and bigger logical diameter. GPGPU-style stream-based or high-throughput CMPs can be used to hide the effect of longer latencies. In this paper, we present layouts for mesh-based underpopulated networks, calculate their wirelength distributions and the overall area. Moreover, we present energy consumption calculations for such networks, and show that while the network part of a CMP system based on underpopulated NOCs can play a major role when considering the chip area and energy consumption, it can be pushed down by increasing the number of dimensions and using meshes instead of tori. We also compare various multidimensional sparse meshlayouts and conclude the 3-dimensional and 4-dimensional sparse meshes to be the most attractive ones for throughput computing",

keywords = "Comparison, layouts, network on chip, sparse networks, throughput computing",

author = "Martti Forsell and V. Lepp{\"a}nen and M. Penttonen",

year = "2011",

doi = "10.1109/DSD.2011.46",

language = "English",

isbn = "978-1-4577-1048-3",

pages = "316--323",

booktitle = "Proceedings",

publisher = "IEEE Institute of Electrical and Electronic Engineers ",

address = "United States",

note = "14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011, DSD 2011 ; Conference date: 31-08-2011 Through 02-09-2011",

}

Forsell, M, Leppänen, V & Penttonen, M 2011, Cost of sparse mesh layouts supporting throughput computing. in Proceedings: 14th Euromicro Conference on Digital System Design, DSD 2011. IEEE Institute of Electrical and Electronic Engineers , pp. 316-323, 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011, Oulu, Finland, 31/08/11. https://doi.org/10.1109/DSD.2011.46

Cost of sparse mesh layouts supporting throughput computing. / Forsell, Martti; Leppänen, V.; Penttonen, M.

Proceedings: 14th Euromicro Conference on Digital System Design, DSD 2011. IEEE Institute of Electrical and Electronic Engineers , 2011. p. 316-323.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific

TY - GEN

T1 - Cost of sparse mesh layouts supporting throughput computing

AU - Forsell, Martti

AU - Leppänen, V.

AU - Penttonen, M.

PY - 2011

Y1 - 2011

N2 - The purpose of this paper is to estimate the cost of utilizing underpopulated, or sparse, networks on chip (NOC) for chip multiprocessors (CMP). In underpopulated NOCs, only a portion of nodes are sources and sinks whereas the rest are simple intermediate nodes increasing communication bandwidth. Compared to dense NOCs, where all nodes can be sources and sinks of communication, the underpopulated NOCs can be scaled so that any degree of communication frequency of nodes can be supported. The drawback of underpopulated NOCs is larger network area and bigger logical diameter. GPGPU-style stream-based or high-throughput CMPs can be used to hide the effect of longer latencies. In this paper, we present layouts for mesh-based underpopulated networks, calculate their wirelength distributions and the overall area. Moreover, we present energy consumption calculations for such networks, and show that while the network part of a CMP system based on underpopulated NOCs can play a major role when considering the chip area and energy consumption, it can be pushed down by increasing the number of dimensions and using meshes instead of tori. We also compare various multidimensional sparse meshlayouts and conclude the 3-dimensional and 4-dimensional sparse meshes to be the most attractive ones for throughput computing

AB - The purpose of this paper is to estimate the cost of utilizing underpopulated, or sparse, networks on chip (NOC) for chip multiprocessors (CMP). In underpopulated NOCs, only a portion of nodes are sources and sinks whereas the rest are simple intermediate nodes increasing communication bandwidth. Compared to dense NOCs, where all nodes can be sources and sinks of communication, the underpopulated NOCs can be scaled so that any degree of communication frequency of nodes can be supported. The drawback of underpopulated NOCs is larger network area and bigger logical diameter. GPGPU-style stream-based or high-throughput CMPs can be used to hide the effect of longer latencies. In this paper, we present layouts for mesh-based underpopulated networks, calculate their wirelength distributions and the overall area. Moreover, we present energy consumption calculations for such networks, and show that while the network part of a CMP system based on underpopulated NOCs can play a major role when considering the chip area and energy consumption, it can be pushed down by increasing the number of dimensions and using meshes instead of tori. We also compare various multidimensional sparse meshlayouts and conclude the 3-dimensional and 4-dimensional sparse meshes to be the most attractive ones for throughput computing

KW - Comparison

KW - layouts

KW - network on chip

KW - sparse networks

KW - throughput computing

U2 - 10.1109/DSD.2011.46

DO - 10.1109/DSD.2011.46

M3 - Conference article in proceedings

SN - 978-1-4577-1048-3

SP - 316

EP - 323

BT - Proceedings

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011

Y2 - 31 August 2011 through 2 September 2011

ER -

Access to Document

10.1109/DSD.2011.46