Abstract
| Original language | English |
|---|---|
| Title of host publication | Proceedings |
| Subtitle of host publication | 14th Euromicro Conference on Digital System Design, DSD 2011 |
| Publisher | Institute of Electrical and Electronic Engineers IEEE |
| Pages | 316-323 |
| ISBN (Print) | 978-1-4577-1048-3 |
| DOIs | |
| Publication status | Published - 2011 |
| MoE publication type | B3 Non-refereed article in conference proceedings |
| Event | 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011 - Oulu, Finland Duration: 31 Aug 2011 → 2 Sep 2011 |
Conference
| Conference | 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011 |
|---|---|
| Abbreviated title | DSD 2011 |
| Country | Finland |
| City | Oulu |
| Period | 31/08/11 → 2/09/11 |
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Keywords
- Comparison
- layouts
- network on chip
- sparse networks
- throughput computing
Cite this
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Cost of sparse mesh layouts supporting throughput computing. / Forsell, Martti; Leppänen, V.; Penttonen, M.
Proceedings: 14th Euromicro Conference on Digital System Design, DSD 2011. Institute of Electrical and Electronic Engineers IEEE, 2011. p. 316-323.Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific
TY - GEN
T1 - Cost of sparse mesh layouts supporting throughput computing
AU - Forsell, Martti
AU - Leppänen, V.
AU - Penttonen, M.
PY - 2011
Y1 - 2011
N2 - The purpose of this paper is to estimate the cost of utilizing underpopulated, or sparse, networks on chip (NOC) for chip multiprocessors (CMP). In underpopulated NOCs, only a portion of nodes are sources and sinks whereas the rest are simple intermediate nodes increasing communication bandwidth. Compared to dense NOCs, where all nodes can be sources and sinks of communication, the underpopulated NOCs can be scaled so that any degree of communication frequency of nodes can be supported. The drawback of underpopulated NOCs is larger network area and bigger logical diameter. GPGPU-style stream-based or high-throughput CMPs can be used to hide the effect of longer latencies. In this paper, we present layouts for mesh-based underpopulated networks, calculate their wirelength distributions and the overall area. Moreover, we present energy consumption calculations for such networks, and show that while the network part of a CMP system based on underpopulated NOCs can play a major role when considering the chip area and energy consumption, it can be pushed down by increasing the number of dimensions and using meshes instead of tori. We also compare various multidimensional sparse meshlayouts and conclude the 3-dimensional and 4-dimensional sparse meshes to be the most attractive ones for throughput computing
AB - The purpose of this paper is to estimate the cost of utilizing underpopulated, or sparse, networks on chip (NOC) for chip multiprocessors (CMP). In underpopulated NOCs, only a portion of nodes are sources and sinks whereas the rest are simple intermediate nodes increasing communication bandwidth. Compared to dense NOCs, where all nodes can be sources and sinks of communication, the underpopulated NOCs can be scaled so that any degree of communication frequency of nodes can be supported. The drawback of underpopulated NOCs is larger network area and bigger logical diameter. GPGPU-style stream-based or high-throughput CMPs can be used to hide the effect of longer latencies. In this paper, we present layouts for mesh-based underpopulated networks, calculate their wirelength distributions and the overall area. Moreover, we present energy consumption calculations for such networks, and show that while the network part of a CMP system based on underpopulated NOCs can play a major role when considering the chip area and energy consumption, it can be pushed down by increasing the number of dimensions and using meshes instead of tori. We also compare various multidimensional sparse meshlayouts and conclude the 3-dimensional and 4-dimensional sparse meshes to be the most attractive ones for throughput computing
KW - Comparison
KW - layouts
KW - network on chip
KW - sparse networks
KW - throughput computing
U2 - 10.1109/DSD.2011.46
DO - 10.1109/DSD.2011.46
M3 - Conference article in proceedings
SN - 978-1-4577-1048-3
SP - 316
EP - 323
BT - Proceedings
PB - Institute of Electrical and Electronic Engineers IEEE
ER -