Counterexample visualization and explanation for function block diagrams

Antti Pakonen; Igor Buzhinsky; Valeriy Vyatkin

doi:10.1109/INDIN.2018.8472025

Counterexample visualization and explanation for function block diagrams

Antti Pakonen, Igor Buzhinsky, Valeriy Vyatkin

Aalto University

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

15 Citations (Scopus)

478 Downloads (Pure)

Abstract

Model checking is a proven, effective method for verifying instrumentation and control system application logics. If a model of the system being verified does not satisfy a specification, the failure scenario is presented to the user as a counterexample trace. Analysis of the counterexample can be time-consuming if the trace is long, the model is large, or the specification is complex. Spurious counterexamples ('false negatives') often exacerbate the problem. In this paper, we present a method that assists in identifying the root of the failure in both the model and the specification, by animating the model of the function block diagram as well as the LTL property. We also introduce a practical tool for visualizing LTL properties by animation and highlighting of important values based on causality. Using 43 actual design issues identified in practical nuclear industry projects, we then evaluate usefulness of the property visualization and explanation features.

Original language	English
Title of host publication	Proceedings of 16th International Conference on Industrial Informatics
Subtitle of host publication	INDIN 2018
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	747-753
Number of pages	7
ISBN (Electronic)	978-1-5386-4829-2, 978-1-5386-4828-5
DOIs	https://doi.org/10.1109/INDIN.2018.8472025
Publication status	Published - 27 Sept 2018
MoE publication type	Not Eligible
Event	16th IEEE International Conference on Industrial Informatics, INDIN 2018 - Porto, Portugal Duration: 18 Jul 2018 → 20 Jul 2018 Conference number: 16

Conference

Conference	16th IEEE International Conference on Industrial Informatics, INDIN 2018
Abbreviated title	INDIN 2018
Country/Territory	Portugal
City	Porto
Period	18/07/18 → 20/07/18

Keywords

Explanation of counterexamples
Formal verification
Model checking
Visualization of counterexamples

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10.1109/INDIN.2018.8472025

Counterexample visualization and explanationAccepted author manuscript, 560 KB

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title = "Counterexample visualization and explanation for function block diagrams",

abstract = "Model checking is a proven, effective method for verifying instrumentation and control system application logics. If a model of the system being verified does not satisfy a specification, the failure scenario is presented to the user as a counterexample trace. Analysis of the counterexample can be time-consuming if the trace is long, the model is large, or the specification is complex. Spurious counterexamples ('false negatives') often exacerbate the problem. In this paper, we present a method that assists in identifying the root of the failure in both the model and the specification, by animating the model of the function block diagram as well as the LTL property. We also introduce a practical tool for visualizing LTL properties by animation and highlighting of important values based on causality. Using 43 actual design issues identified in practical nuclear industry projects, we then evaluate usefulness of the property visualization and explanation features.",

keywords = "Explanation of counterexamples, Formal verification, Model checking, Visualization of counterexamples",

author = "Antti Pakonen and Igor Buzhinsky and Valeriy Vyatkin",

note = "Funding Information: ACKNOWLEDGMENT This work has been funded by the Finnish Research Programme on Nuclear Power Plant Safety 2015-2018 (SAFIR 2018), and by the Ministry of Education and Science of the Russian Federation, project RFMEFI58716X0032. Publisher Copyright: {\textcopyright} 2018 IEEE. Copyright: Copyright 2018 Elsevier B.V., All rights reserved.; 16th IEEE International Conference on Industrial Informatics, INDIN 2018, INDIN 2018 ; Conference date: 18-07-2018 Through 20-07-2018",

year = "2018",

month = sep,

day = "27",

doi = "10.1109/INDIN.2018.8472025",

language = "English",

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booktitle = "Proceedings of 16th International Conference on Industrial Informatics",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

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Pakonen, A, Buzhinsky, I & Vyatkin, V 2018, Counterexample visualization and explanation for function block diagrams. in Proceedings of 16th International Conference on Industrial Informatics: INDIN 2018., 8472025, IEEE Institute of Electrical and Electronic Engineers, pp. 747-753, 16th IEEE International Conference on Industrial Informatics, INDIN 2018, Porto, Portugal, 18/07/18. https://doi.org/10.1109/INDIN.2018.8472025

Counterexample visualization and explanation for function block diagrams. / Pakonen, Antti; Buzhinsky, Igor; Vyatkin, Valeriy.
Proceedings of 16th International Conference on Industrial Informatics: INDIN 2018. IEEE Institute of Electrical and Electronic Engineers, 2018. p. 747-753 8472025.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

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AU - Buzhinsky, Igor

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N1 - Conference code: 16

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Y1 - 2018/9/27

N2 - Model checking is a proven, effective method for verifying instrumentation and control system application logics. If a model of the system being verified does not satisfy a specification, the failure scenario is presented to the user as a counterexample trace. Analysis of the counterexample can be time-consuming if the trace is long, the model is large, or the specification is complex. Spurious counterexamples ('false negatives') often exacerbate the problem. In this paper, we present a method that assists in identifying the root of the failure in both the model and the specification, by animating the model of the function block diagram as well as the LTL property. We also introduce a practical tool for visualizing LTL properties by animation and highlighting of important values based on causality. Using 43 actual design issues identified in practical nuclear industry projects, we then evaluate usefulness of the property visualization and explanation features.

AB - Model checking is a proven, effective method for verifying instrumentation and control system application logics. If a model of the system being verified does not satisfy a specification, the failure scenario is presented to the user as a counterexample trace. Analysis of the counterexample can be time-consuming if the trace is long, the model is large, or the specification is complex. Spurious counterexamples ('false negatives') often exacerbate the problem. In this paper, we present a method that assists in identifying the root of the failure in both the model and the specification, by animating the model of the function block diagram as well as the LTL property. We also introduce a practical tool for visualizing LTL properties by animation and highlighting of important values based on causality. Using 43 actual design issues identified in practical nuclear industry projects, we then evaluate usefulness of the property visualization and explanation features.

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BT - Proceedings of 16th International Conference on Industrial Informatics

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ER -

Counterexample visualization and explanation for function block diagrams

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